Search results for "Parallel processors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Enrico Angelelli, Maria Grazia Speranza, Zsolt Tuza	Semi-On-line Scheduling on Two Parallel Processors with an Upper Bound on the Items.	Algorithmica	2003	DBLP DOI BibTeX RDF	Two parallel processors, Semi-on-line, Scheduling, Competitive analysis
3	Richard Games, Arkady Kanevsky, Peter C. Krupp, Leonard Monk	Real-time communications scheduling for massively parallel processors. (PDF / PS)	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	real-time communications scheduling, computationally intensive, lifecycle costs, large-scale scientific computing, software challenges, processing nodes, real-time application benchmarks, scheduling, performance evaluation, fault tolerance, real-time systems, parallel processing, multiprocessor interconnection networks, multiprocessor interconnection networks, real-time scheduling, processor scheduling, real-time applications, massively parallel processors, multi-level security
2	Francesca Palumbo, Danilo Pani, Luigi Raffo, Simone Secchi	A Surface Tension and Coalescence Model for Dynamic Distributed Resources Allocation in Massively Parallel Processors on-Chip.	NICSO	2007	DBLP DOI BibTeX RDF
2	Mauro Dell'Amico, Manuel Iori, Silvano Martello	Heuristic Algorithms and Scatter Search for the Cardinality Constrained P\|\|Cmax Problem.	J. Heuristics	2004	DBLP DOI BibTeX RDF	scheduling, parallel processors, scatter search, cardinality constraint
2	Sumit Ghosh	P2EDAS: Asynchronous, Distributed Event Driven Simulation Algorithm with Inconsistent Event Preemption for Accurate Execution of VHDL Descriptions on Parallel Processors.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	simulation of hardware descriptions, inertial delays, descheduling, anticipatory scheduling, preemption of inconsistent events, parallel processing, VLSI, distributed algorithms, discrete event simulation, VHDL, Digital simulation, logic simulation, event driven simulation, timing semantics
2	Aneesh Aggarwal, Manoj Franklin	Putting Data Value Predictors to Work in Fine-Grain Parallel Processors.	HiPC	2001	DBLP DOI BibTeX RDF
2	Marco Ferretti	Multi-Media Extensions in Super-Pipelined Micro-Architectures. A New Case for SIMD Processing?	CAMP	2000	DBLP DOI BibTeX RDF	super-pipelined microarchitectures, general purpose microprocessors, Von-Neumann paradigm, image processing, parallel architectures, associated memory, instruction set architectures, massively parallel processors, multimedia extensions, SIMD processing
2	David R. Martinez	Application of Parallel Processors to Real-Time Sensor Array Processing. (PDF / PS)	IPPS/SPDP	1999	DBLP DOI BibTeX RDF
2	Kai Hwang, Choming Wang, Cho-Li Wang, Zhiwei Xu	Resource Scaling Effects on MPP Performance: The STAP Benchmark Implications.	IEEE Trans. Parallel Distrib. Syst.	1999	DBLP DOI BibTeX RDF	SPMD parallelism, ASCI program, STAP benchmark, phase-parallel model, latency and bandwidth, supercomputer performance, Massively parallel processors, scalability analysis
2	Sanjeev Banerjia, William A. Havanki, Thomas M. Conte	Treegion Scheduling for Highly Parallel Processors.	Euro-Par	1997	DBLP DOI BibTeX RDF
2	Chi-Hsiang Yeh, Behrooz Parhami	Swapped networks: unifying the architectures and algorithms of a wide class of hierarchical parallel processors. (PDF / PS)	ICPADS	1996	DBLP DOI BibTeX RDF	swapped networks, hierarchical parallel processors, high-dimensional meshes, generalized hypercubes, fixed-degree building blocks, parallel algorithms, interconnection networks, parallel architectures, parallel architectures, hypercubes, multiprocessor interconnection networks
2	Ishfaq Ahmad, Yu-Kwong Kwok, Min-You Wu	Analysis, evaluation, and comparison of algorithms for scheduling task graphs on parallel processors.	ISPAN	1996	DBLP DOI BibTeX RDF	edge-weighted directed acyclic graph, bounded number of processors scheduling, arbitrary processor network, scheduling, scheduling, parallel programming, processor scheduling, data flow graphs, task graphs, parallel processors, dataflow graph
2	Klaus E. Schauser, Chris J. Scheiman, J. Mitchell Ferguson, Paul Z. Kolano	Exploiting the Capabilities of Communications Co-Processors. (PDF / PS)	IPPS	1996	DBLP DOI BibTeX RDF	inter-computer links, communications coprocessor architecture, dedicated hardware support, user-level message handlers, Split-C, message handling code, Meiko CS-2 platform, synchronization, parallel architectures, local area networks, synchronisation, flexibility, coprocessors, computational power, massively parallel processors, workstation networks, active messages, electronic messaging
2	Zhiwei Xu, Kai Hwang	MPPs and clusters for scalable computing.	ISPAN	1996	DBLP DOI BibTeX RDF	scalable parallel computing, Cray T3D/T3E, ASCI TeraFLOPS, performance evaluation, scalability, parallel architectures, reconfigurable architectures, clusters of workstations, Intel Paragon, Intel, massively parallel processors, performance attributes, scalable computing, MPPs, IBM SP2
2	Péter Kacsuk, Günter Haring, Szabolcs Ferenczi, Georg Pigel, Gábor Dózsa, Tibor Fadgyas	Visual Parallel Programming in Monads-DPV.	PDP	1996	DBLP DOI BibTeX RDF	layered visual parallel programming approach, Monads-DPV, very high level parallel programs, parallel programming, object-oriented programming, case studies, visual programming, visual languages, object oriented model, graphical notation, massively parallel processors
2	Kai Hwang, Zhiwei Xu, Masahiro Arakawa	Benchmark Evaluation of the IBM SP2 for Parallel Signal Processing.	IEEE Trans. Parallel Distrib. Syst.	1996	DBLP DOI BibTeX RDF	adaptive sensor array processing, STAP benchmarks, performance evaluation, scalability, Message passing, real-time applications, data parallelism, programmability, massively parallel processors
2	Sumit Ghosh, Meng-Lin Yu	An Asynchronous Distributed Approach for the Simulation of Behavior-Level Models on Parallel Processors.	IEEE Trans. Parallel Distrib. Syst.	1995	DBLP DOI BibTeX RDF
2	Isabelle Attali, Denis Caromel, Andrew L. Wendelborn	From a formal dynamic semantics of Sisal to a Sisal environment.	HICSS	1995	DBLP DOI BibTeX RDF	formal dynamic semantics, Sisal environment, Sisal 2.0, structural operational style, Typoi inference rules, Centaur system, generic specification environment, strongly typed language, single assignment language, vector machines, formal specification, parallel programming, software tools, multiprocessors, programming environments, parallel languages, parallel processors, Sisal, Natural Semantics, formal definition, dataflow machines
2	Christian Clémençon, Akiyoshi Endo, Josef Fritscher, Andreas Müller, Roland Rühl, Brian J. N. Wylie	The "Annai" environment for portable distributed parallel programming.	HICSS	1995	DBLP DOI BibTeX RDF	Annai environment, portable distributed parallel programming environment, distributed memory parallel processors, tool prototypes, functionality enhancements, High Performance Fortran compiler, unstructured problem parallelization, performance analyzer, source-level debugger, common user interface, low-level machine interface, target hardware architecture, dynamic data distributions, high-level data-parallel programming, low-level message-passing programming, interactive performance monitor, user interfaces, parallel programming, Message Passing Interface, software tools, message passing, FORTRAN, programming environments, feedback, program compilers, distributed memory systems, software performance evaluation, portability, program debugging, software portability, program diagnostics, application developers, language extensions, performance results
2	Ernst W. Mayr	Scheduling interval orders in parallel.	HICSS	1995	DBLP DOI BibTeX RDF	interval order scheduling, interval representations, transitively oriented digraph, undirected chordal complement, identical parallel processors, minimal length schedule, scheduling distance computation subroutine, incremental version, empty slots, interval order precedence constraints, scheduling, parallel algorithms, parallel algorithm, computational complexity, concurrency control, directed graphs, partial orders, NP-complete problems, deadlines, execution time, minimisation, interval graphs, optimal schedule, release times, NC-algorithm, CREW-PRAM, task systems
2	Pierre E. Sorel, Mariano G. Fernandez, Sumit Ghosh	A Dynamic Debugger for Asynchronous Distributed Algorithms.	IEEE Software	1994	DBLP DOI BibTeX RDF	dynamic debugger, asynchronous distributed algorithms, LPdbx, distributed runtime debugger, loosely coupled parallel processors, iconic interface, program suspension, pointer references, banking applications, transportation applications, shareware, data structures, data structures, distributed algorithms, graphical user interfaces, program debugging, transportation, breakpoints, bank data processing, global variables
2	Naoki Hamanaka, Junji Nakagoshi, Teruo Tanaka	Reducing Network Hardware Quantity by Employing Multi-Processor Cluster Structure in Distributed Memory Parallel Processors.	CONPAR	1992	DBLP DOI BibTeX RDF
2	Chien-Min Wang, Sheng-De Wang	Efficient Processor Assignment Algorithms and Loop Transformations for Executing Nested Parallel Loops on Multiprocessors.	IEEE Trans. Parallel Distrib. Syst.	1992	DBLP DOI BibTeX RDF	processor assignment algorithms, nested parallel loops, performance, parallel algorithms, parallel programming, multiprocessors, program compilers, loop transformations, parallel processors, parallel execution
2	John Zahorjan, Edward D. Lazowska, Derek L. Eager	The Effect of Scheduling Discipline on Spin Overhead in Shared Memory Parallel Systems.	IEEE Trans. Parallel Distrib. Syst.	1991	DBLP DOI BibTeX RDF	scheduling discipline, spin overhead, shared memory parallel systems, busywaiting, data-dependent execution, memoryarchitecture, scheduling, performance evaluation, parallel machines, spinning, multiprogramming, parallel processors
2	Roland Rühl, Marco Annaratone	Parallelization of FORTRAN code on distributed-memory parallel processors.	ICS	1990	DBLP DOI BibTeX RDF	FORTRAN
2	Marco Annaratone, Claude Pommerell, Roland Rühl	Interprocessor Communication Speed and Performance in Distributed-memory Parallel Processors.	ISCA	1989	DBLP DOI BibTeX RDF
2	Tsutomu Hoshino, Toshio Kawai, Tomonori Shirakawa, Junichi Higashino, Akira Yamaoka, Hachidai Ito, Takashi Sato, Kazuo Sawada	PACS: A Parallel Microprocessor Array for Scientific Calculations	ACM Trans. Comput. Syst.	1983	DBLP DOI BibTeX RDF	highly parallel processors, multimicroprocessors, nearest neighbor communication, scientific calculation, distributed systems, parallel algorithms, synchronization, multiprocessors, performance measurement, supercomputer, parallel language, processor architecture, MIMD, array processors, multiprocessing, parallel processors
2	Ronald H. Perrott	Language design approaches for parallel processors.	CONPAR	1981	DBLP DOI BibTeX RDF
1	Rafal Rózycki, Jan Weglarz	Power-aware scheduling of preemptable jobs on identical parallel processors to meet deadlines.	European Journal of Operational Research	2012	DBLP DOI BibTeX RDF
1	Wancheng Zhang, Qiuyu Fu, Nan-Jian Wu	A Programmable Vision Chip Based on Multiple Levels of Parallel Processors.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Ami Marowka	Back to Thin-Core Massively Parallel Processors.	IEEE Computer	2011	DBLP DOI BibTeX RDF
1	Eric Angel, Evripidis Bampis, Fadi Kacem, Dimitrios Letsios	Speed Scaling on Parallel Processors with Migration	CoRR	2011	DBLP BibTeX RDF
1	Robert Fasthuber, Min Li, David Novo, Praveen Raghavan, Liesbet Van der Perre, Francky Catthoor	Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors.	Signal Processing Systems	2011	DBLP DOI BibTeX RDF
1	Francesca Palumbo, Danilo Pani, Andrea Deidda, Luigi Raffo	Towards self-adaptive networks on chip for massively parallel processors: multilevel quality of service programmability.	Conf. Computing Frontiers	2011	DBLP DOI BibTeX RDF
1	Carlos Domínguez, Houcine Hassan, José Albaladejo, Maria Marco, Alfons Crespo	Emotional Contribution Process Implementations on Parallel Processors.	ICA3PP	2011	DBLP DOI BibTeX RDF
1	Anne Benoit, Paul Renaud-Goud, Yves Robert	On the Performance of Greedy Algorithms for Power Consumption Minimization.	ICPP	2011	DBLP DOI BibTeX RDF	Independent jobs, Power consumption minimization, Greedy algorithm, Parallel processors
1	Daniel R. Johnson, Matthew R. Johnson, John H. Kelm, William Tuohy, Steven S. Lumetta, Sanjay J. Patel	Rigel: A 1, 024-Core Single-Chip Accelerator Architecture.	IEEE Micro	2011	DBLP DOI BibTeX RDF	Multiple data-stream architectures (multiprocessors), multiple data processors, single-chip multiprocessors, parallel architectures, multicore, parallel processors, multiple instruction
1	Jie Cheng	Programming Massively Parallel Processors. A Hands-on Approach.	Scalable Computing: Practice and Experience	2010	DBLP BibTeX RDF
1	David Blair Kirk, Wen-mei W. Hwu	Programming Massively Parallel Processors - A Hands-on Approach.		2010	RDF
1	Ashley Reid, James E. Gain, Michelle Kuttel	Dynamic load balancing of Lattice Boltzmann free-surface fluid animations.	Afrigraph	2010	DBLP DOI BibTeX RDF
1	Sunpyo Hong, Hyesoon Kim	An integrated GPU power and performance model.	ISCA	2010	DBLP DOI BibTeX RDF	GPU architecture, performance, energy, analytical model, CUDA, power estimation
1	Hritam Dutta, Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich, Bernard Pottier	A holistic approach for tightly coupled reconfigurable parallel processors.	Microprocessors and Microsystems - Embedded Hardware Design	2009	DBLP DOI BibTeX RDF
1	Wieslaw Kubiak, Djamal Rebaine, Chris N. Potts	Optimality of HLF for scheduling divide-and-conquer UET task graphs on identical parallel processors.	Discrete Optimization	2009	DBLP DOI BibTeX RDF
1	Hou-Biao Li, Ting-Zhu Huang, Yong Zhang, Xing-Ping Liu, Hong Li	On some new approximate factorization methods for block tridiagonal matrices suitable for vector and parallel processors.	Mathematics and Computers in Simulation	2009	DBLP DOI BibTeX RDF
1	Johnny C. Ho, Tzu-Liang (Bill) Tseng, Alex J. Ruiz-Torres, Francisco J. López	Minimizing the normalized sum of square for workload deviations on m parallel processors.	Computers & Industrial Engineering	2009	DBLP DOI BibTeX RDF
1	Mahmut T. Kandemir, Yuanrui Zhang, Sai Prashanth Muralidhara, Ozcan Ozturk, Sri Hari Krishna Narayanan	Slicing based code parallelization for minimizing inter-processor communication.	CASES	2009	DBLP DOI BibTeX RDF	automatic code parallelization, code analysis and optimization, iteration space slicing, parallelizing compilers
1	David P. Luebke	Graphics hardware & GPU computing: past, present, and future.	Graphics Interface	2009	DBLP DOI BibTeX RDF
1	Sunpyo Hong, Hyesoon Kim	An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness.	ISCA	2009	DBLP DOI BibTeX RDF	GPU architecture, warp level parallelism, analytical model, performance estimation, cuda, memory level parallelism
1	John Owens	HCW 2009 keynote talk: GPU computing: Heterogeneous computing for future systems.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Jeff A. Stuart, John D. Owens	Message passing on data-parallel architectures.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Antoine Joux, Stefan Lucks	Improved Generic Algorithms for 3-Collisions.	ASIACRYPT	2009	DBLP DOI BibTeX RDF	multicollision, random map, memory-efficient, cryptanalysis, parallel implementation
1	A. W. Roscoe, P. J. Armstrong, Pragyesh	Local Search in Model Checking.	ATVA	2009	DBLP DOI BibTeX RDF
1	Nguyen-Khang Pham, Annie Morin, Patrick Gros	Accelerating Image Retrieval Using Factorial Correspondence Analysis on GPU.	CAIP	2009	DBLP DOI BibTeX RDF	Factorial correspondence analysis, CUBLAS, Image retrieval, GPU, CUDA, SIFT
1	Luke J. Gosink, Kesheng Wu, E. Wes Bethel, John D. Owens, Kenneth I. Joy	Data Parallel Bin-Based Indexing for Answering Queries on Multi-core Architectures.	SSDBM	2009	DBLP DOI BibTeX RDF
1	Anna Nepomniaschaya	Efficient Implementation of the Italiano Algorithms for Updating the Transitive Closure on Associative Parallel Processors.	Fundam. Inform.	2008	DBLP BibTeX RDF
1	Michael J. Flynn, Robert G. Dimond, Oskar Mencer, Oliver Pell	Finding Speedup in Parallel Processors.	ISPDC	2008	DBLP DOI BibTeX RDF
1	Michael Garland	Sparse matrix computations on manycore GPU's.	DAC	2008	DBLP DOI BibTeX RDF	parallel programming, GPU computing, shortest path algorithms, data-parallel algorithms, sparse matrix-vector multiplication
1	Han Yu	Optimizing task schedules using an artificial immune system approach.	GECCO	2008	DBLP DOI BibTeX RDF	parallel computing, artificial immune systems, task scheduling
1	Zhen Liu, Srinivasan Parthasarathy 0002, Anand Ranganathan, Hao Yang	A generic flow algorithm for shared filter ordering problems.	PODS	2008	DBLP DOI BibTeX RDF	flow maximization, shared filter ordering, parallel, query optimization
1	Kai Shen, Alex Zhang, Terence Kelly, Christopher Stewart	Operational analysis of processor speed scaling.	SPAA	2008	DBLP DOI BibTeX RDF	acpi, datacenter-on-chip, p-states, scheduling, performance modeling, power, multicore, capacity planning, queuing, dynamic resource allocation, multi-processor, operational analysis, internet servers
1	Claude Kauffmann, Nicolas Piche	Cellular automaton for ultra-fast watershed transform on GPU.	ICPR	2008	DBLP DOI BibTeX RDF
1	Yongjin Yeom, Yongkuk Cho, Moti Yung	High-Speed Implementations of Block Cipher ARIA Using Graphics Processing Units.	MUE	2008	DBLP DOI BibTeX RDF	GPU, implementation, block cipher, GPGPU, Graphics Processor, ARIA
1	Guilin Chen, Mahmut T. Kandemir	Compiler-Directed Code Restructuring for Improving Performance of MPSoCs.	IEEE Trans. Parallel Distrib. Syst.	2008	DBLP DOI BibTeX RDF
1	Francesca Palumbo, Simone Secchi, Danilo Pani, Luigi Raffo	A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs.	SAMOS	2008	DBLP DOI BibTeX RDF	Dual-mode switching, Non-exclusive switching, Networks on Chip, Circuit switching
1	Jonathan L. Bentz, Ryan M. Olson, Mark S. Gordon, Michael W. Schmidt, Ricky A. Kendall	Coupled cluster algorithms for networks of shared memory parallel processors.	Computer Physics Communications	2007	DBLP DOI BibTeX RDF
1	Giuseppe Paletta, Paolamaria Pietramala	A New Approximation Algorithm for the Nonpreemptive Scheduling of Independent Jobs on Identical Parallel Processors.	SIAM J. Discrete Math.	2007	DBLP DOI BibTeX RDF
1	Orhan Gemikonakli, Glenford E. Mapp, Enver Ever, Dhawal N. Thakker	Modelling Network Memory Servers with Parallel Processors, Break-downs and Repairs.	Annual Simulation Symposium	2007	DBLP DOI BibTeX RDF
1	Susanne Albers, Fabian Müller, Swen Schmelzer	Speed scaling on parallel processors.	SPAA	2007	DBLP DOI BibTeX RDF	approximation algorithms, energy efficiency, NP-completeness, online algorithms, multiprocessor scheduling
1	Giovanni Danese, Francesco Leporati, Marco Bera, Mauro Giachero, Nelson Nazzicari, Alvaro Spelgatti	An Accelerator for Physics Simulations.	Computing in Science and Engineering	2007	DBLP DOI BibTeX RDF	Monte Carlo dynamics, parallel processors, gate arrays, instruction set design
1	Bruno Galilée, Franck Mamalet, Marc Renaudin, Pierre-Yves Coulon	Parallel Asynchronous Watershed Algorithm-Architecture.	IEEE Trans. Parallel Distrib. Syst.	2007	DBLP DOI BibTeX RDF	Asynchronous algorithm-architecture, performance evaluation, image segmentation, hill-climbing, correctness proof, parallel processors, watershed
1	Andrea Marongiu, Luca Benini, Mahmut T. Kandemir	Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms.	CASES	2007	DBLP DOI BibTeX RDF	code parallelization, MPSoCs, barrier synchronization
1	Matthew B. Dwyer, Sebastian G. Elbaum, Suzette Person, Rahul Purandare	Parallel Randomized State-Space Search.	ICSE	2007	DBLP DOI BibTeX RDF
1	S. Govind, R. Govindarajan, Joy Kuri	Packet Reordering in Network Processors.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Kevin Schaffer, Robert A. Walker	A Prototype Multithreaded Associative SIMD Processor.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Liping Xue, Mahmut T. Kandemir, Guilin Chen, Feihui Li, Ozcan Ozturk, Rajaraman Ramanarayanan, Balaji Vaidyanathan	Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Majid Khabbazian, T. Aaron Gulliver, Vijay K. Bhargava	Double Point Compression with Applications to Speeding Up Random Point Multiplication.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	point compression, fast computation, parallel processing, Cryptography, elliptic curves, point multiplication
1	Nicholas Mastronarde, Mihaela van der Schaar	A Queuing-Theoretic Approach to Task Scheduling and Processor Selection for Video-Decoding Applications.	IEEE Transactions on Multimedia	2007	DBLP DOI BibTeX RDF
1	Kimmo U. Järvinen, Juha Forsten, Jorma Skyttä	FPGA Design of Self-certified Signature Verification on Koblitz Curves.	CHES	2007	DBLP DOI BibTeX RDF
1	Mostafa I. Soliman, Sanguthevar Rajasekaran, Reda A. Ammar	A Block JRS Algorithm for Highly Parallel Computation of SVDs.	HPCC	2007	DBLP DOI BibTeX RDF
1	Farshad Safaei, Mahmood Fathy, Ahmad Khonsari, N. Talebanfard	On Disconnection Node Failure and Stochastic Static Resilience of P2P Communication Networks.	ICCSA	2007	DBLP DOI BibTeX RDF
1	Sungchan Park, Chao Chen, Hong Jeong	VLSI Architecture for MRF Based Stereo Matching.	SAMOS	2007	DBLP DOI BibTeX RDF
1	Adam Janiak, Tomasz Krysiak	Single processor scheduling with job values depending on their completion times.	J. Scheduling	2007	DBLP DOI BibTeX RDF	Single processor, Job value, Heuristic, NP-hardness, Polynomial time
1	D. Doreen Hephzibah Miriam, T. Srinivasan, R. Deepa	An Efficient SRA Based Isomorphic Task Allocation Scheme for k - ary n - cube Massively Parallel Processors.	PARELEC	2006	DBLP DOI BibTeX RDF	Full subcube recognition, k-ary n-cube systems, isomorphic partitioning, processor allocation
1	Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd M. Austin	Ultra low-cost defect protection for microprocessor pipelines.	ASPLOS	2006	DBLP DOI BibTeX RDF	defect-protection, reliability, pipelines, low-cost
1	Yanan Shen, Rongcai Zhao, Jianmin Pang	Automatic code generation of data decomposition.	Infoscale	2006	DBLP DOI BibTeX RDF	message-passing, parallelizing compilers, linear inequalities, data decomposition
1	Michael D. McCool, Kevin Wadleigh, Brent Henderson, Hsin-Ying Lin	Poster reception - Performance evaluation of GPUs using the RapidMind development platform.	SC	2006	DBLP DOI BibTeX RDF
1	Ming-Hua Hsieh	A new approach for parallel steady-state simulations.	Winter Simulation Conference	2006	DBLP DOI BibTeX RDF
1	Aydin O. Balkan, Gang Qu, Uzi Vishkin	A Mesh-of-Trees Interconnection Network for Single-Chip Parallel Processing.	ASAP	2006	DBLP DOI BibTeX RDF
1	Alireza Mahdian, Hamid Khalili, Ehsan Nourbakhsh, Mohammad Ghodsi	Web Graph Compression by Edge Elimination.	DCC	2006	DBLP DOI BibTeX RDF
1	Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin, Suleyman Tosun	Multi-Level On-Chip Memory Hierarchy Design for Embedded Chip Multiprocessors.	ICPADS	2006	DBLP DOI BibTeX RDF
1	Liping Xue, Mahmut T. Kandemir, Guangyu Chen, Taylan Yemliha	SPM Conscious Loop Scheduling for Embedded Chip Multiprocessors.	ICPADS	2006	DBLP DOI BibTeX RDF	SPM (Scratch-Pad Memory), dynamic loop scheduling, parallelization, compiler, CMP (chip multiprocessor), data locality
1	Kevin J. Barker, Scott Pakin, Darren J. Kerbyson	A Performance Model of the Krak Hydrodynamics Application.	ICPP	2006	DBLP DOI BibTeX RDF
1	Julius Fabian Ohmer, Frédéric Maire, Ross Brown	Real-Time Tracking with Non-Rigid Geometric Templates Using the GPU.	CGIV	2006	DBLP DOI BibTeX RDF
1	Hadi Esmaeilzadeh, Pooya Saeedi, Babak Nadjar Araabi, Caro Lucas, Seid Mehdi Fakhraie	Neural network stream processing core (NnSP) for embedded systems.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Zhiyong He, Sébastien Roy 0002, Paul Fortier	Encoder architecture with throughput over 10 Gbit/sec for quasi-cyclic LDPC codes.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Ebru Celikel, Jean Davidson, Colin Kern	Parallel performance of DES in ECB mode.	ISCN	2006	DBLP DOI BibTeX RDF
1	Ozcan Ozturk, G. Chen, Mahmut T. Kandemir, Mustafa Karaköy	An Integer Linear Programming Based Approach to Simultaneous Memory Space Partitioning and Data Allocation for Chip Multiprocessors.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Cruz Izu, José Miguel-Alonso, José A. Gregorio	Effects of Injection Pressure on Network Throughput.	PDP	2006	DBLP DOI BibTeX RDF
1	Paulo Moises Vidica, Gina Maira Barbosa de Oliveira	Cellular Automata-Based Scheduling: A New Approach to Improve Generalization Ability of Evolved Rules.	SBRN	2006	DBLP DOI BibTeX RDF
1	Nuha A. S. Alwan	A Fully Pipelined Systolic Array for Sinusoidal Sequence Generation.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Trigonometric series, sinusoidal sequence generation, pipelining, systolic arrays