Search results for "Partha Pratim Pande"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Turbo Majumder, Souradip Sarkar, Partha Pratim Pande, Ananth Kalyanaraman	NoC-Based Hardware Accelerator for Breakpoint Phylogeny.	IEEE Trans. Computers	2012	DBLP DOI BibTeX RDF
1	Sujay Deb, Kevin Chang, Amlan Ganguly, Xinmin Yu, Christof Teuscher, Partha Pratim Pande, Deuk Hyoun Heo, Benjamin Belzer	Design of an efficient NoC architecture using millimeter-wave wireless links.	ISQED	2012	DBLP DOI BibTeX RDF
1	Sujay Deb, Kevin Chang, Miralem Cosic, Amlan Ganguly, Partha Pratim Pande, Deuk Hyoun Heo, Benjamin Belzer	CMOS compatible many-core noc architectures with multi-channel millimeter-wave wireless links.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Amlan Ganguly, Kevin Chang, Sujay Deb, Partha Pratim Pande, Benjamin Belzer, Christof Teuscher	Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	on-chip antenna, wireless communication, Network-on-chip, multicore, small-world network
1	Amlan Ganguly, Paul Wettin, Kevin Chang, Partha Pratim Pande	Complex network inspired fault-tolerant NoC architectures with wireless links.	NOCS	2011	DBLP BibTeX RDF
1	Partha Pratim Pande, Fabien Clermidy, Diego Puschini, Imen Mansouri, Paul Bogdan, Radu Marculescu, Amlan Ganguly	Sustainability through massively integrated computing: Are we ready to break the energy efficiency wall for single-chip platforms?	DATE	2011	DBLP DOI BibTeX RDF
1	Amlan Ganguly, Partha Pratim Pande, Benjamin Belzer, Alireza Nojeh	A Unified Error Control Coding Scheme to Enhance the Reliability of a Hybrid Wireless Network-on-Chip.	DFT	2011	DBLP DOI BibTeX RDF
1	Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pratim Pande, Ananth Kalyanaraman	Network-on-Chip Hardware Accelerators for Biological Sequence Alignment.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	DNA/protein sequence alignment, on-chip parallelism, bioinformatics, Network-on-chip, hardware acceleration
1	Partha Pratim Pande, Sriram R. Vangal	Guest Editors' Introduction: Promises and Challenges of Novel Interconnect Technologies.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF
1	Sujay Deb, Amlan Ganguly, Kevin Chang, Partha Pratim Pande, Benjamin Belzer, Deuk Hyoun Heo	Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnects.	ASAP	2010	DBLP DOI BibTeX RDF
1	Souradip Sarkar, Turbo Majumder, Ananth Kalyanaraman, Partha Pratim Pande	Hardware accelerators for biocomputing: A survey.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Sujay Deb, Kevin Chang, Amlan Ganguly, Partha Pratim Pande	Comparative performance evaluation of wireless and optical NoC architectures.	SoCC	2010	DBLP DOI BibTeX RDF
1	Radu Marculescu, Christof Teuscher, Partha Pratim Pande	Unconventional fabrics, architectures, and models for future multi-core systems.	CODES+ISSS	2010	DBLP DOI BibTeX RDF
1	Brett Feero, Partha Pratim Pande	Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
1	Amlan Ganguly, Partha Pratim Pande, Benjamin Belzer	Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NOC Interconnects.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Amlan Ganguly, Kevin Chang, Partha Pratim Pande, Benjamin Belzer, Alireza Nojeh	Performance evaluation of wireless networks on chip architectures.	ISQED	2009	DBLP DOI BibTeX RDF
1	Partha Pratim Pande, Amlan Ganguly, Haibo Zhu, Cristian Grecu	Energy reduction through crosstalk avoidance coding in networks on chip.	Journal of Systems Architecture - Embedded Systems Design	2008	DBLP DOI BibTeX RDF
1	Amlan Ganguly, Partha Pratim Pande, Benjamin Belzer, Cristian Grecu	Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Crosstalk avoidance, Multiple error correction, Joint codes, Low power, Network on Chip, Transient errors
1	Partha Pratim Pande, Amlan Ganguly, Benjamin Belzer, Alireza Nojeh, André Ivanov	Novel interconnect infrastructures for massive multicore chips - an overview.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Cristian Grecu, André Ivanov, Resve A. Saleh, Partha Pratim Pande	Testing Network-on-Chip Communication Fabrics.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Brett Feero, Partha Pratim Pande	Performance Evaluation for Three-Dimensional Networks-On-Chip.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Amlan Ganguly, Partha Pratim Pande, Benjamin Belzer, Cristian Grecu	Addressing Signal Integrity in Networks on Chip Interconnects through Crosstalk-Aware Double Error Correction Coding.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Cristian Grecu, André Ivanov, Partha Pratim Pande, Axel Jantsch, Erno Salminen, Ümit Y. Ogras, Radu Marculescu	Towards Open Network-on-Chip Benchmarks.	NOCS	2007	DBLP DOI BibTeX RDF	performance evaluation, metrics, benchmarks, networks-on-chip
1	Haibo Zhu, Partha Pratim Pande, Cristian Grecu	Performance Evaluation of Adaptive Routing Algorithms for achieving Fault Tolerance in NoC Fabrics.	ASAP	2007	DBLP DOI BibTeX RDF
1	Partha Pratim Pande, Amlan Ganguly, Brett Feero, Cristian Grecu	Applicability of Energy Efficient Coding Methodology to Address Signal Integrity in 3D NoC Fabrics.	IOLTS	2007	DBLP DOI BibTeX RDF
1	Cristian Grecu, Lorena Anghel, Partha Pratim Pande, André Ivanov, Resve Saleh	Essential Fault-Tolerance Metrics for NoC Infrastructures.	IOLTS	2007	DBLP DOI BibTeX RDF
1	Jabulani Nyathi, Souradip Sarkar, Partha Pratim Pande	Multiple clock domain synchronization for network on chip architectures.	SoCC	2007	DBLP DOI BibTeX RDF
1	Partha Pratim Pande, Haibo Zhu, Amlan Ganguly, Cristian Grecu	Energy Reduction through Crosstalk Avoidance Coding in NoC Paradigm.	DSD	2006	DBLP DOI BibTeX RDF	crosstalk avoidance codes, interconnect energy, networks on chip, crosstalk, wormhole switching
1	Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh	BIST for Network-on-Chip Interconnect Infrastructures.	VTS	2006	DBLP DOI BibTeX RDF	interconnect infrastructure, unicast test, multicast test, built-in self-test, network-on-chip
1	Partha Pratim Pande, Amlan Ganguly, Brett Feero, Benjamin Belzer, Cristian Grecu	Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding.	DFT	2006	DBLP DOI BibTeX RDF
1	Cristian Grecu, André Ivanov, Res Saleh, Partha Pratim Pande	NoC Interconnect Yield Improvement Using Crosspoint Redundancy.	DFT	2006	DBLP DOI BibTeX RDF
1	Cristian Grecu, André Ivanov, Res Saleh, Egor S. Sogomonyan, Partha Pratim Pande	On-line Fault Detection and Location for NoC Interconnects.	IOLTS	2006	DBLP DOI BibTeX RDF
1	Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh	Timing analysis of network on chip architectures for MP-SoC platforms.	Microelectronics Journal	2005	DBLP DOI BibTeX RDF
1	Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh	Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	system-on-chip, Network-on-chip, interconnect architecture, MP-SoC, infrastructure IP
1	Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, Giovanni De Micheli	Design, Synthesis, and Test of Networks on Chips.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	Reliability, VLSI, Automatic synthesis, VLSI Systems, Testing and Fault-Tolerance
1	Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Res Saleh	Effect of traffic localization on energy dissipation in NoC-based interconnect.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Cristian Grecu, Partha Pratim Pande, Baosheng Wang, André Ivanov, Res Saleh	Methodologies and Algorithms for Testing Switch-Based NoC Interconnects.	DFT	2005	DBLP DOI BibTeX RDF
1	Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh	A Scalable Communication-Centric SoC Interconnect Architecture.	ISQED	2004	DBLP DOI BibTeX RDF	switch-based interconnect, butterfly fat-tree, global wire delay, System on chip, interconnect architecture, timing closure
1	Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh	Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	BFT, scalability, pipelining, bus, MP-SoC
1	Partha Pratim Pande, Cristian Grecu, André Ivanov	High-Throughput Switch-Based Interconnect for Future SoCs.	IWSOC	2003	DBLP DOI BibTeX RDF	SoC, Wormhole Routing, Virtual Channels, Interconnect Architecture
1	Partha Pratim Pande, Cristian Grecu, André Ivanov, Res Saleh	Design of a switch for network on chip applications.	ISCAS	2003	DBLP DOI BibTeX RDF

Publications of "Partha Pratim Pande" ( http://dblp.L3S.de/Authors/Partha_Pratim_Pande )