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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 34 occurrences of 29 keywords
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Results
Found 51 publication records. Showing 51 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Roopak Sinha, Partha S. Roop, Zoran Salcic, Samik Basu |
Correct-by-construction multi-component SoC design.  |
DATE  |
2012 |
DBLP BibTeX RDF |
|
| 1 | Ivan Radojevic, Zoran Salcic, Partha S. Roop |
Design of Distributed Heterogeneous Embedded Systems in DDFCharts. |
IEEE Trans. Parallel Distrib. Syst. |
2011 |
DBLP DOI BibTeX RDF |
modeling, specification languages, Formal languages, heterogeneous systems |
| 1 | Syed Adeel Ali, Partha S. Roop, Ian Warren, Zeeshan Ejaz Bhatti |
Unified management of control flow and data mismatches in web service composition. |
SOSE |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Simon Yuan, Li Hsien Yoong, Partha S. Roop |
Compiling Esterel for Multi-core Execution. |
DSD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Matthew Kuo, Roopak Sinha, Partha S. Roop |
Efficient WCRT analysis of synchronous programs using reachability. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sidharta Andalam, Partha S. Roop, Alain Girault |
Pruning infeasible paths for tight WCRT analysis of synchronous programs. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Li Hsien Yoong, Partha S. Roop |
Verifying IEC 61499 Function Blocks Using Esterel. |
Embedded Systems Letters |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Avinash Malik, Zoran Salcic, Partha S. Roop, Alain Girault |
SystemJ: A GALS language for system level design. |
Computer Languages, Systems & Structures |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sidharta Andalam, Partha S. Roop, Alain Girault |
Predictable multithreading of embedded applications using PRET-C. |
MEMOCODE |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sidharta Andalam, Partha S. Roop, Alain Girault |
Deterministic, predictable and light-weight multithreading using PRET-C. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Simon Yuan, Li Hsien Yoong, Sidharta Andalam, Partha S. Roop, Zoran Salcic |
A New Multithreaded Architecture Supporting Direct Execution of Esterel. |
EURASIP J. Emb. Sys. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Avinash Malik, Zoran A. Salcic, Partha S. Roop |
SystemJ compilation using the tandem virtual machine approach. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
SystemJ, compilation, virtual machines, System-level design, esterel |
| 1 | Li Hsien Yoong, Partha S. Roop, Valeriy Vyatkin, Zoran A. Salcic |
A Synchronous Approach for IEC 61499 Function Block Implementation. |
IEEE Trans. Computers |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Simon Yuan, Sidharta Andalam, Li Hsien Yoong, Partha S. Roop, Zoran A. Salcic |
STARPro - A new multithreaded direct execution platform for Esterel. |
Electr. Notes Theor. Comput. Sci. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Partha S. Roop, Alain Girault, Roopak Sinha, Gregor Goessler |
Specification Enforcing Refinement for Convertibility Verification. |
ACSD |
2009 |
DBLP DOI BibTeX RDF |
forced simulation, discrete controller synthesis, Protocol conversion |
| 1 | Partha S. Roop, Sidharta Andalam, Reinhard von Hanxleden, Simon Yuan, Claus Traulsen |
Tight WCRT analysis of synchronous C programs. |
CASES |
2009 |
DBLP DOI BibTeX RDF |
precision timed machines, model checking, synchronous languages, static timing analysis |
| 1 | Roopak Sinha, Partha S. Roop, Samik Basu, Zoran Salcic |
Multi-clock Soc design using protocol conversion. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Gareth Shaw, Partha S. Roop, Zoran Salcic |
A Hierarchical and Concurrent Approach for IEC 61499 Function Blocks. |
ETFA |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Roopak Sinha, Partha S. Roop, Samik Basu |
SoC Design Approach Using Convertibility Verification. |
EURASIP J. Emb. Sys. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Roopak Sinha, Partha S. Roop, Samik Basu |
A Model Checking Approach to Protocol Conversion. |
Electr. Notes Theor. Comput. Sci. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Roopak Sinha, Partha S. Roop, Samik Basu |
A Module Checking Based Converter Synthesis Approach for SoCs. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
protocol mismatches, mod- ule checking, protocol conversion |
| 1 | Samik Basu, Partha S. Roop, Roopak Sinha |
Local Module Checking for CTL Specifications. |
Electr. Notes Theor. Comput. Sci. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hai-Feng Guo, Miao Liu, Partha S. Roop, C. R. Ramakrishnan, I. V. Ramakrishnan |
Precise specification matching for adaptive reuse in embedded systems. |
J. Applied Logic |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ivan Radojevic, Zoran A. Salcic, Partha S. Roop |
McCharts and Multiclock FSMs for modeling large scale systems. |
MEMOCODE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Zoran A. Salcic, Dong Hui, Partha S. Roop, Morteza Biglari-Abhari |
HiDRA - A reactive multiprocessor architecture for heterogeneous embedded systems. |
Microprocessors and Microsystems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ivan Radojevic, Zoran A. Salcic, Partha S. Roop |
Modeling Embedded Systems: From SystemC and Esterel to DFCharts. |
IEEE Design & Test of Computers |
2006 |
DBLP DOI BibTeX RDF |
models of computation (MoC), specification, SystemC, heterogeneous systems, Esterel |
| 1 | Flavius Gruian, Partha S. Roop, Zoran A. Salcic, Ivan Radojevic |
The SystemJ approach to system-level design. |
MEMOCODE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Zoran A. Salcic, Flavius Gruian, Partha S. Roop, Alif Wahid |
A Scheduler Support Unit for Reactive Microprocessors. |
RTCSA |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ivan Radojevic, Zoran A. Salcic, Partha S. Roop |
Design of Heterogeneous Embedded Systems Using DFCharts Model of Computation. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ivan Radojevic, Zoran A. Salcic, Partha S. Roop |
A New Model for Heterogeneous Embedded Systems - What Esterel and SyncCharts Need to Become a Suitable Specification Platform. |
International Journal of Software Engineering and Knowledge Engineering |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Roopak Sinha, Partha S. Roop, Bakhadyr Khoussainov |
Adaptive Verification using Forced Simulation. |
Electr. Notes Theor. Comput. Sci. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Robi Malik, Partha S. Roop |
Adaptive Techniques for Specification Matching in Embedded Systems: A Comparative Study. |
IFM |
2005 |
DBLP DOI BibTeX RDF |
embedded systems, Formal verification, finite-state machines, bisimulation, supervisory control, specification matching |
| 1 | Zoran A. Salcic, Dong Hui, Partha S. Roop, Morteza Biglari-Abhari |
REMIC: design of a reactive embedded microprocessor core. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Ivan Radojevic, Zoran A. Salcic, Partha S. Roop |
Modelling Heterogeneous Embedded Systems in DFCarts. |
FDL |
2005 |
DBLP BibTeX RDF |
|
| 1 | Zoran A. Salcic, Partha S. Roop, Morteza Biglari-Abhari, Abbas Bigdeli |
REFLIX: a processor core with native support for control-dominated embedded applications. |
Microprocessors and Microsystems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Partha S. Roop, Zoran A. Salcic, M. W. Sajeewa Dayaratne |
Towards direct execution of esterel programs on reactive processors. |
EMSOFT |
2004 |
DBLP DOI BibTeX RDF |
ARE-Bench Auckland reactive benchmark, direct ESTEREL execution, reactive processor architectures |
| 1 | Zoran A. Salcic, Partha S. Roop |
Customizing Processor Cores to Support Reactivity. |
ERSA |
2004 |
DBLP BibTeX RDF |
|
| 1 | Zoran A. Salcic, Partha S. Roop, Dong Hui, Ivan Radojevic |
HiDRA: A New Architecture for Heterogeneous Embedded Systems. |
ESA/VLSI |
2004 |
DBLP BibTeX RDF |
|
| 1 | Partha S. Roop, Zoran A. Salcic, Morteza Biglari-Abhari, Abbas Bigdeli |
A New Reactive Processor with Architectural Support for Control Dominated Embedded Systems. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Rick Mugridge, Bruce A. MacDonald, Partha S. Roop |
A Customer Test Generator for Web-Based Systems. |
XP |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Rick Mugridge, Bruce A. MacDonald, Partha S. Roop, Ewan D. Tempero |
Five Challenges in Teaching XP. |
XP |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Zoran A. Salcic, Partha S. Roop, Morteza Biglari-Abhari, Abbas Bigdeli |
REFLIX: A Processor Core for Reactive Embedded Applications. |
FPL |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Partha S. Roop, Arcot Sowmya, S. Ramesh |
k-time Forced Simulation: A Formal Verification Technique for IP Reuse. |
ICCD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Partha S. Roop, Arcot Sowmya, S. Ramesh |
Forced simulation: A technique for automating component reuse in embedded systems. |
ACM Trans. Design Autom. Electr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
forced simulation, embedded systems, verification, Component reuse, simulation relation, interface generation |
| 1 | Partha S. Roop, Arcot Sowmya, S. Ramesh |
A formal approach to component based development of synchronous programs. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Partha S. Roop, Arcot Sowmya, S. Ramesh |
Automated Component Adaptation by Forced Simulation. |
ACAC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Partha S. Roop, Arcot Sowmya, S. Ramesh |
Automatic Component Matching Using Forced Simulation. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Partha S. Roop, Arcot Sowmya |
Hidden time model for specification and verification of embedded systems. |
ECRTS |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Partha S. Roop, Arcot Sowmya |
CFSMcharts: A New Language for Microprocessor Based system Design. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Raj S. Mitra, Partha S. Roop, Anupam Basu |
A new algorithm for implementation of design functions by available devices. |
IEEE Trans. VLSI Syst. |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Raj S. Mitra, Partha S. Roop, Anupam Basu |
Implementation of design functions by available devices: a new algorithm. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
design functions, available devices, function behaviors, mapping process, VLSI, VLSI, CAD, finite state machines, finite state machines, logic CAD, circuit CAD, logic partitioning, logic partitioning |
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