Search results for "Partial product"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Robert Michael Owens, Raminder Singh Bajwa, Mary Jane Irwin	Reducing the number of counters needed for integer multiplication.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	counting circuits, reasonably small integers, partial product accumulation, aperiodic convolution, convolution algorithms, partial product formulation, fairly large integers, digital arithmetic, multiplying circuits, counters, integer multiplication
2	Chua-Chin Wang, Gang-Neng Sung	Low-Power Multiplier Design Using a Bypassing Technique.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Low power multiplier, Timing control, Partial product, Bypassing
2	Ivan D. Castellanos, James E. Stine	Compressor trees for decimal partial product reduction.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	VLSI, decimal arithmetic
2	Chao-Yue Lai, Chung-Yang Huang, Kei-Yong Khoo	Improving Constant-Coefficient Multiplier Verification by Partial Product Identification.	DATE	2008	DBLP DOI BibTeX RDF
2	James E. Stine, Jeff M. Blank	Partial Product Reduction for Parallel Cubing.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Higinio Mora Mora, Jerónimo Mora Pascual, José-Luis Sánchez-Romero, F. Pujol López	Partial Product Reduction Based on Look-Up Tables.	VLSI Design	2006	DBLP DOI BibTeX RDF
2	Mark A. Erle, Eric M. Schwarz, Michael J. Schulte	Decimal Multiplication with Efficient Partial Product Generation.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
2	Shuo Zhou, Bo Yao, Jianhua Liu, Chung-Kuan Cheng	Integrated algorithmic logical and physical design of integer multiplier.	ASP-DAC	2005	DBLP DOI BibTeX RDF	booth, interconnect, partial product, TDM
2	Peter-Michael Seidel, Lee D. McFearin, David W. Matula	Secondary Radix Recodings for Higher Radix Multipliers.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	recoding, high radix, digit set, mixed radix representation, partial product reduction, Booth recoding, Binary multiplication
2	Johann Großschädl	A unified radix-4 partial product generator for integers and binary polynomials.	ISCAS	2002	DBLP DOI BibTeX RDF
2	Hak-soo Yu, Jacob A. Abraham	An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation.	VLSI Design	2002	DBLP DOI BibTeX RDF	3-bit-scan, power-delay-area tradeoffs, synchronous sequential, multiplier, partial product
2	Rong Lin	Parallel Multiplier Designs Utilizing A Non-Binary Logic Scheme.	EUROMICRO	2000	DBLP DOI BibTeX RDF	parallel counter and compressor, low power high performance CMOS circuit design, VLSI design, Arithmetic circuit, partial product reduction
2	Abdeslam En-Nouaary, Ferhat Khendek, Rachida Dssouli	Testing embedded real-time systems.	RTCSA	2000	DBLP DOI BibTeX RDF	embedded real-time system testing, system correctness, implementation testing, real-time components, communicating timed input-output automata, testing in context, testing in isolation, timed Wp-method, embedded systems, formal specification, formal verification, program testing, conformance testing, conformance testing, timing constraints, safety-critical systems, test case generation, safety-critical software, automata theory, concurrent processes, communicating processes, system quality, partial product
2	Charles U. Martel, Vojin G. Oklobdzija, R. Ravi, Paul F. Stelling	Design Strategies for Optimal Multiplier Circuits.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	Algorithms, Circuit design, Partial product reduction, Multiplier design
2	Peter T. Johnstone	Fibrations and partial products in a 2-category.	Applied Categorical Structures	1993	DBLP DOI BibTeX RDF	partial product, Fibration, 2-category
1	Chiu-wei Pan, Zhao Wang, Yuanchen Song, Carl Sechen	Power efficient partial product compression.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Kuan Jen Lin, Yu Chan Chiu, Tzu-Hao Lin	A decimal squarer with efficient partial product generation.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Shreesha Srinath, Katherine Compton	Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks.	FPGA	2010	DBLP DOI BibTeX RDF	asymmetric multipliers, composable multipliers, multiplier design
1	Bijoy A. Jose, Damu Radhakrishnan	Redundant binary partial product generators for compact accumulation in Booth multipliers.	Microelectronics Journal	2009	DBLP DOI BibTeX RDF
1	Shiann-Rong Kuang, Jiun-Ping Wang, Cang-Yuan Guo	Modified Booth Multipliers With a Regular Partial Product Array.	IEEE Trans. on Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Meng-Lin Hsia, Oscal T.-C. Chen	Low-power Multiplier Optimized by Partial-Product Summation and Adder Cells.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Higinio Mora Mora, Jerónimo Mora Pascual, José-Luis Sánchez-Romero, Juan Manuel García Chamizo	Partial product reduction by using look-up tables for M×N multiplier.	Integration	2008	DBLP DOI BibTeX RDF
1	Luigi Dadda, Alberto Nannarelli	A variant of a radix-10 combinational multiplier.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Rizwan Mudassir, Mohab Anis, Javid Jaffari	Switching activity reduction in low power Booth multiplier.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Gang-Neng Sung, Yan-Jhin Ciou, Chua-Chin Wang	A power-aware 2-dimensional bypassing multiplier using cell-based design flow.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Li-Rong Wang, Yi-Wei Chiu, Chia-Lin Hu, Ming-Hsien Tu, Shyh-Jye Jou, Chung-Len Lee	A reconfigurable MAC architecture implemented with mixed-Vt standard cell library.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Krishnan Ramakrishnan, R. Rajaraman, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin, Kenan Unlu	Hierarchical Soft Error Estimation Tool (HSEET).	ISQED	2008	DBLP DOI BibTeX RDF	Reliability, Soft Errors, Flip-Flop, Combinational Logic
1	Sabyasachi Das, Sunil P. Khatri	An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Sabyasachi Das, Sunil P. Khatri	A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Shahid Rizwan	Retimed Decomposed Serial Berlekamp-Massey (BM) Architecture for High-Speed Reed-Solomon Decoding.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Robert T. Grisamore, Earl E. Swartzlander Jr.	Negative Save Sign Extension for Multi-term Adders and Multipliers.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	adder trees, multi-term adders, two’s complement arithmetic, sign extension, multipliers
1	Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Oscar Gustafsson	Transition-activity aware design of reduction-stages for parallel multipliers.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	power consumption, parallel multiplier, partial product reduction, transition activity
1	Mark A. Erle, Michael J. Schulte, Brian J. Hickmann	Decimal Floating-Point Multiplication Via Carry-Save Addition.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
1	Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi	A New Family of High.Performance Parallel Decimal Multipliers.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
1	Sun-Ah Hong, Yong-Eun Kim, Jin-Gyun Chung, Sung-Chul Lee	Efficient Squarer Design Using Group Partial Products.	SiPS	2007	DBLP DOI BibTeX RDF
1	Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas	Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Mohammad D. Mottaghi, Ali Afzali-Kusha, Zainalabedin Navabi	ByZFAD: a low switching activity architecture for shift-and-add multipliers.	SBCCI	2006	DBLP DOI BibTeX RDF	adder bypass, byZFAD, hot-block ring counter, shiftand-add multiplier, low-power, switching activity
1	Hayssam El-Razouk, Zine Abid	Area and Power Efficient Array and Tree Multipliers.	CCECE	2006	DBLP DOI BibTeX RDF
1	Viay Holimath, Javier D. Bruguera	A Linear Convergent Functional Iterative DivisionWithout a Look-Up Table.	DSD	2006	DBLP DOI BibTeX RDF
1	Haridimos T. Vergos, Costas Efstathiou	Novel Modulo 2n + 1 Multipliers.	DSD	2006	DBLP DOI BibTeX RDF
1	Henrik Eriksson, Per Larsson-Edefors, Mary Sheeran, Magnus Själander, D. Johansson, M. Scholin	Multiplier reduction tree with logarithmic logic depth and regular connectivity.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Shiann Shiun Jeng, Hsing-Chen Lin, Shu-Ming Chang	FPGA implementation of FIR filter using M-bit parallel distributed arithmetic.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Chua-Chin Wang, Gang-Neng Sung	A Low-Power 2-Dimensional Bypassing Multiplier Using 0.35 um CMOS Technology.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Jung-Yup Kang, Jean-Luc Gaudiot	A Simple High-Speed Multiplier Design.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Booth, modified Booth, Multiplier, partial products
1	Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert	Toward architecture-based test-vector generation for timing verification of fast parallel multipliers.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Lu Yang, Biplab Kumer Sarker, Virendrakumar C. Bhavsar, Harold Boley	A Weighted-Tree Simplicity Algorithm for Similarity Matching of Partial Product Descriptions.	IASSE	2005	DBLP BibTeX RDF
1	M. Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José C. Monteiro	Design of a radix-2m hybrid array multiplier using carry save adder format.	SBCCI	2005	DBLP DOI BibTeX RDF	hybrid multiplier, low power, carry save adder
1	Yajuan He, Chip-Hong Chang, Jiangmin Gu, Hossam A. H. Fahmy	A novel covalent redundant binary Booth encoder.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Albert Danysh, Dimitri Tan	Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	data-path design, multiply-accumulate, Booth, Wallace, unsigned, multimedia, VLSI, Parallel, MAC, SIMD, vector, fixed-point, multiplier, high-speed arithmetic, signed, integer
1	Zhijun Huang, Milos D. Ercegovac	High-Performance Low-Power Left-to-Right Array Multiplier Design.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Left-to-right array multiplier, tree multiplier, layout regularity, low-power design, high-performance design
1	Hanho Lee	Reconfigurable Power-Aware Scalable Booth Multiplier.	KES	2005	DBLP DOI BibTeX RDF
1	Leonardo Londero de Oliveira, Cristiano Santos, Daniel Lima Ferrão, Eduardo A. C. da Costa, José C. Monteiro, João Baptista dos Santos Martins, Sergio Bampi, Ricardo Augusto da Luz Reis	A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
1	Jinn-Shyan Wang, Chien-Nan Kuo, Tsung-Han Yang	Low-power fixed-width array multipliers.	ISLPED	2004	DBLP DOI BibTeX RDF	fixed-width multiplier, left-to-right multiplier, reduced-width multiplier, low power
1	Hans Eberle, Nils Gura, Sheueling Chang Shantz, Vipul Gupta, Leonard Rarick, Shreyas Sundaram	A Public-Key Cryptographic Processor for RSA and ECC.	ASAP	2004	DBLP DOI BibTeX RDF
1	Jung-Yup Kang, Jean-Luc Gaudiot	A Fast and Well-Structured Multiplier.	DSD	2004	DBLP DOI BibTeX RDF
1	Shankar Krithivasan, Michael J. Schulte, John Glossner	A Subword-Parallel Multiplication and Sum-of-Squares Unit.	ISVLSI	2004	DBLP DOI BibTeX RDF
1	Troy D. Townsend, Peter Celinski, Said F. Al-Sarawi, Michael J. Liebelt	Hybrid Parallel Counters - Domino and Threshold Logic.	ISVLSI	2004	DBLP DOI BibTeX RDF
1	Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos	Modified Booth Modulo 2n-1 Multipliers.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Mersenne arithmetic, one's complement arithmetic, Booth multipliers, VLSI design, Residue Number System
1	Mary Sheeran	Generating Fast Multipliers Using Clever Circuits.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Francesca Cagliari, Sandra Mantovani	Injective Hulls of T0 Topological Fibre Spaces.	Applied Categorical Structures	2003	DBLP DOI BibTeX RDF	injective hull, continuous lattice, exponentiable morphism, pullback complement, partial product
1	Dimitri Tan, Albert Danysh, Michael J. Liebelt	Multiple-Precision Fixed-Point Vector Multiply-Accumulator Using Shared Segmentation.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
1	B. R. Lee, Neil Burgess	Improved Small Multiplier Based Multiplication, Squaring and Division.	FCCM	2003	DBLP DOI BibTeX RDF
1	Hwang-Cherng Chow, I-Chyn Wey	A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Junhyung Um, Taewhan Kim	Synthesis of arithmetic circuits considering layout effects.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	T. Sansaloni, Javier Valls, Keshab K. Parhi	Digit-Serial Complex-Number Multipliers on FPGAs.	VLSI Signal Processing	2003	DBLP DOI BibTeX RDF	complex-number multipliers, digit-serial arithmetic, FPGA, Booth recoding
1	Junhyung Um, Taewhan Kim	Layout-aware synthesis of arithmetic circuits.	DAC	2002	DBLP DOI BibTeX RDF	layout, high performance, carry-save-adder
1	Jun-ni Ohban, Vasily G. Moshnyaga, Koji Inoue	Multiplier energy reduction through bypassing of partial products.	APCCAS	2002	DBLP DOI BibTeX RDF
1	Alexander Taubin, Karl Fant, John McCardle	Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image Processing.	ICCD	2002	DBLP DOI BibTeX RDF
1	Rong Lin	Bit-Matrix Decomposition and Dynamic Reconfiguration: A Unified Arithmetic Processor Architecture, Design and Test. (PDF / PS)	IPDPS	2002	DBLP DOI BibTeX RDF
1	A. Aggoun, A. Farwan, M. K. Ibrahim	A radix-2n vector inner product.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Ohsang Kwon, Kevin J. Nowka, Earl E. Swartzlander Jr.	A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells.	VLSI Signal Processing	2002	DBLP DOI BibTeX RDF	3:2 counter, 4:2 compressor, 5:3 compressor, 5:2 compressor, MAC, multiplier
1	Braden Phillips	Optimised Squaring of Long Integers Using Precomputed Partial Products.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
1	Peter-Michael Seidel, Lee D. McFearin, David W. Matula	Binary Multiplication Radix-32 and Radix-256.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
1	Henrik Eriksson, Per Larsson-Edefors, William P. Marnane	A regular parallel multiplier which utilizes multiple carry-propagate adders.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Natalia Kazakova, R. Sung, Nelson G. Durdle, Martin Margala, Julien Lamoureux	Fast and low-power inner product processor.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka	A 16-Bit x 16-Bit MAC Design Using Fast 5: 2 Compressors.	ASAP	2000	DBLP DOI BibTeX RDF	3:2 counter, 4:2 compressor, 5:2 compressor, MAC, multiplier
1	Wen-Chang Yeh, Chein-Wei Jen	High-Speed Booth Encoded Parallel Multiplier Design.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Final adder, multiple-level conditional-sum adder and parallel multiplier, Booth encoding
1	Rong Lin, Kevin E. Kerr, André S. Botha	A Novel Approach for CMOS Parallel Counter Design.	EUROMICRO	1999	DBLP DOI BibTeX RDF	parallel counter and compressor, low power high speed CMOS circuit design, VLSI design, Arithmetic circuit, partial product reduction
1	Paul D. Fiore	Parallel Multiplication Using Fast Sorting Networks.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Dadda's counter, 4:2 compressor, bitonic sorting network, Parallel multiplier, partial product reduction
1	Jeng-Jong J. Lue, Dhananjay S. Phatak	Area x Delay (A T) Efficient Multiplier Based on an Intermediate Hybrid Signed-Digit (HSD-1) Representation.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF
1	M. A. Sacristán, María Victoria Rodellar Biarge, Antonio Diaz, V. Garcia, Pedro Gómez Vilda	A Reusable Inner Product Unit for DSP Applications.	EUROMICRO	1999	DBLP DOI BibTeX RDF
1	Avinash K. Gautam, V. Visvanathan, S. K. Nandy	Automatic Generation of Tree Multipliers Using Placement-Driven Netlists.	ICCD	1999	DBLP DOI BibTeX RDF
1	Sung-Ho Baik, Kyung-Nam Han, E. Yoon	A 230 MHz 8 tap programmable FIR filter using redundant binary number system.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Kei-Yong Khoo, Chao-Liang Chen, Alan N. Willson Jr.	A CMOS pipelined carry-save array using true single-phase single-transistor-latch clocking.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.	Improved-Booth encoding for low-power multipliers.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Paul F. Stelling, Charles U. Martel, Vojin G. Oklobdzija, R. Ravi	Optimal Circuits for Parallel Multipliers.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	algorithms, circuit design, partial product reduction, Multiplier design
1	Paul F. Stelling, Vojin G. Oklobdzija	Implementing Multiply-Accumulate Operation in Multiplication Time.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	multiply-accumulate operation, multiplication time, optimal delays, instruction time, optimal multiply-accumulate circuit, RISC CPU, partial product reduction tree, final adder, digital signal processing, power savings, multiplying circuits, circuit design, VLSI circuits, parallel multiplier, processor performance, video applications, graphics applications, clock speed
1	Stuart F. Oberman, Hesham A. Al-Twaijry, Michael J. Flynn	The SNAP Project: Design of Floating Point Arithmetic Unit.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	performance-area tradeoffs, computer arithmetic, multiplication, division, Addition, floating point unit
1	Yongjin Jeong, Wayne P. Burleson	VLSI array algorithms and architectures for RSA modular multiplication.	IEEE Trans. VLSI Syst.	1997	DBLP DOI BibTeX RDF
1	Vojin G. Oklobdzija, David Villeger, Simon S. Liu	A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF
1	R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili	Energy delay analysis of partial product reduction methods for parallel multiplier implementation.	ISLPED	1996	DBLP DOI BibTeX RDF	SPICE
1	S. Cui, Neil Burgess, Michael J. Liebelt, Kamran Eshraghian	A GaAs IEEE Floating Point Standard Single Precision Multiplier.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	floating point multiplier, rounding algorithm, modified carry save array, GaAs technology
1	S. Cui, Neil Burgess, Michael J. Liebelt, Kamran Eshraghian	A 32-bit GaAs IEEE floating point multiplier using Trailing-1's rounding algorithm.	Electronic Technology Directions	1995	DBLP DOI BibTeX RDF
1	D. V. Poornaiah, P. V. Ananda Mohan	Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture.	VLSI Design	1995	DBLP DOI BibTeX RDF	concurrent multiplier-accumulator architecture, second order modified Booth algorithm, sign extension bits minimization algorithm, sign-bit updating algorithm, multi-bit recoded parallel multipliers, computation time reduction, CMOS standard cell technology, 35 ns, 50 pF, parallel algorithms, VLSI, VLSI, parallel architectures, digital arithmetic, multiplication, CMOS logic circuits, multiplying circuits, accumulation, 1 micron
1	Eric M. Schwarz, Michael J. Flynn	Hardware starting approximation for the square root operation.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
1	Todd C. Marek	A new simulator workbench for comparing SIMD processing element architectures.	ACM Southeast Regional Conference	1992	DBLP DOI BibTeX RDF
1	Çetin Kaya Koç, Ching Yu Hung	Bit-level systolic arrays for modular multiplication.	VLSI Signal Processing	1991	DBLP DOI BibTeX RDF	sign estimation, scheduling, systolic array, modular multiplication, carry save adders
1	Erik Meineche Schmidt, Michael I. Schwartzbach	An Imperative Type Hierarchy with Partial Products.	MFCS	1989	DBLP DOI BibTeX RDF
1	S. A. Kent	A High-Speed Threshold Gate Multiplier.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	High-speed adder, threshold logic, propagation delay, partial product, parallel multiplication
1	William J. Stenzel, William J. Kubitz, Gilles H. Garcia	A Compact High-Speed Parallel Multiplication Scheme.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	generalized counters, partial-product reduction, fast multipliers, Binary multiplication