Search results for "Patrick Girard"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Hassan Salmani, Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty, Patrick Girard, Xiaoqing Wen	Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez	Analysis and Fault Modeling of Actual Resistive Defects in ATMEL [InlineMediaObject not available: see fulltext.] eFlash Memories.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Junxia Ma, Mohammad Tehranipoor, Patrick Girard	A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	J. Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, G. Prenat, Jérémy Alvarez-Herault, Ken Mackay	Impact of resistive-open defects on the heat current of TAS-MRAM architectures.	DATE	2012	DBLP BibTeX RDF
1	Sybille Caffiau, Patrick Girard, Laurent Guittet, X. Blanc	Vérification de cohérence entre modèles de tâches et de dialogue en conception centrée-utilisateur.	Ingénierie des Systèmes d'Information	2011	DBLP BibTeX RDF
1	Thomas Lachaume, Patrick Girard, Laurent Guittet, Allan Fousse	Prototypage basé sur les modèles de tâches: une étude pilote.	IHM	2011	DBLP DOI BibTeX RDF
1	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	On using address scrambling to implement defect tolerance in SRAMs.	ITC	2011	DBLP DOI BibTeX RDF
1	Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel	Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Nabil Badereddine	Failure Analysis and Test Solutions for Low-Power SRAMs.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Kohei Miyase, X. Wen	Power-Aware Test Pattern Generation for At-Speed LOS Testing.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich	A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor	Power-aware test generation with guaranteed launch safety for at-speed scan testing.	VTS	2011	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Matteo Sonza Reorda, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch	On the Modeling of Gate Delay Faults by Means of Transition Delay Faults.	DFT	2011	DBLP DOI BibTeX RDF
1	Luigi Dilillo, Alberto Bosio, Miroslav Valka, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel	Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector.	DFT	2011	DBLP DOI BibTeX RDF
1	Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel	A study of path delay variations in the presence of uncorrelated power and ground supply noise.	DDECS	2011	DBLP DOI BibTeX RDF
1	Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez	On using a SPICE-like TSTAC™ eFlash model for design and test.	DDECS	2011	DBLP DOI BibTeX RDF
1	Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling.	DDECS	2011	DBLP DOI BibTeX RDF
1	Jeremy Seligman, Fenrong Liu, Patrick Girard	Logic in the Community.	ICLA	2011	DBLP DOI BibTeX RDF
1	Sybille Caffiau, Dominique L. Scapin, Patrick Girard, Mickaël Baron, Francis Jambon	Increasing the expressive power of task analysis: Systematic comparison and empirical assessment of tool-supported task models.	Interacting with Computers	2010	DBLP DOI BibTeX RDF
1	Adrien Marion, Patrick Girard, Didier Vray	Quaternionic Spatiotemporal Filtering for Dense Motion Field Estimation in Ultrasound Imaging.	EURASIP J. Adv. Sig. Proc.	2010	DBLP DOI BibTeX RDF
1	Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Xiaoqing Wen, Nisar Ahmed	A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor	High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel	A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	Diagnosis, fault modeling, fault simulation, circuit simulation, critical path tracing
1	Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed	Is test power reduction through X-filling good enough?	ITC	2010	DBLP DOI BibTeX RDF
1	D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich	Parity prediction synthesis for nano-electronic gate designs.	ITC	2010	DBLP DOI BibTeX RDF
1	Jean Marc Gallière, Paolo Rech, Patrick Girard, Luigi Dilillo	A roaming memory test bench for detecting particle induced SEUs.	ITC	2010	DBLP DOI BibTeX RDF
1	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	Impact of Resistive-Bridging Defects in SRAM Core-Cell.	DELTA	2010	DBLP DOI BibTeX RDF	core-cell, resistive-bridging defects, SRAM
1	Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda	An Exact and Efficient Critical Path Tracing Algorithm.	DELTA	2010	DBLP DOI BibTeX RDF	Fault models, Fault Simulation, Critical Path Tracing
1	Paolo Rech, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Luigi Dilillo	A Memory Fault Simulator for Radiation-Induced Effects in SRAMs.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
1	Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer	A Comprehensive System-on-Chip Logic Diagnosis.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
1	Junxia Ma, Jeremy Lee, Mohammad Tehranipoor, Nisar Ahmed, Patrick Girard	Pattern grading for testing critical paths considering power supply noise and crosstalk using a layout-aware quality metric.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	pattern grading, crosstalk, signal integrity, power supply noise, path delay test
1	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	A statistical simulation method for reliability analysis of SRAM core-cells.	DAC	2010	DBLP DOI BibTeX RDF	SRAM core-cell, Monte-Carlo, reliability analysis
1	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	Setting test conditions for improving SRAM reliability.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez	A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen	Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes.	DDECS	2010	DBLP DOI BibTeX RDF
1	Johan van Benthem, Patrick Girard, Olivier Roy	Everything Else Being Equal: A Modal Logic for Ceteris Paribus Preferences.	J. Philosophical Logic	2009	DBLP DOI BibTeX RDF
1	Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch	Is triple modular redundancy suitable for yield improvement?	IET Computers & Digital Techniques	2009	DBLP DOI BibTeX RDF
1	Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Analysis of Resistive-Open Defects in SRAM Sense Amplifiers.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash.	J. Electronic Testing	2009	DBLP DOI BibTeX RDF
1	Youssef Benabboud, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute	A case study on logic diagnosis for System-on-Chip.	ISQED	2009	DBLP DOI BibTeX RDF
1	Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard	NAND flash testing: A preliminary study on actual defects.	ITC	2009	DBLP DOI BibTeX RDF
1	Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer	Delay Fault Diagnosis in Sequential Circuits.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Christophe Kolski, Peter Forbrig, Bertrand David, Patrick Girard, Chi Dung Tran, Houcine Ezzedine	Agent-Based Architecture for Interactive System Design: Current Approaches, Perspectives and Evaluation.	HCI	2009	DBLP DOI BibTeX RDF	evaluation, Human-computer interaction, design, CSCW, agent-based systems, Architecture model
1	Sybille Caffiau, Patrick Girard, Laurent Guittet, Dominique L. Scapin	Hierarchical Structure: A Step for Jointly Designing Interactive Software Dialog and Task Model.	HCI	2009	DBLP DOI BibTeX RDF	task models, iterative design, dialog
1	Sybille Caffiau, Patrick Girard, Dominique L. Scapin, Laurent Guittet, Loé Sanou	Formally Expressing the Users' Objects World in Task Models.	TAMODIA	2009	DBLP DOI BibTeX RDF
1	Alexandre Ney, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin	A new design-for-test technique for SRAM core-cell stability faults.	DATE	2009	DBLP BibTeX RDF
1	Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute	Comprehensive bridging fault diagnosis based on the SLAT paradigm.	DDECS	2009	DBLP DOI BibTeX RDF
1	Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda	An efficient fault simulation technique for transition faults in non-scan sequential circuits.	DDECS	2009	DBLP DOI BibTeX RDF
1	Patrick Girard, Jeremy Seligman	An Analytic Logic of Aggregation.	ICLA	2009	DBLP DOI BibTeX RDF	preference logic, lexicographic aggregation, hybrid modal logic, analytic proof theory, sequent calculus
1	Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault	A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	DfT, Scan, Test data compression, Low power testing
1	Nicola Nicolici, Patrick Girard	Guest Editorial.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF
1	Loé Sanou, Patrick Girard, Laurent Guittet, Sybille Caffiau	Tester la conformité d'une IHM à son modèle de tâches.	IHM	2008	DBLP DOI BibTeX RDF
1	Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	SoC Yield Improvement: Redundant Architectures to the Rescue?	ITC	2008	DBLP DOI BibTeX RDF
1	Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs.	ITC	2008	DBLP DOI BibTeX RDF
1	Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Improving Diagnosis Resolution without Physical Information.	DELTA	2008	DBLP DOI BibTeX RDF	Logic Diagnosis, Fault Modeling, Path Tracing
1	Sybille Caffiau, Patrick Girard, Dominique L. Scapin, Laurent Guittet, Loé Sanou	Assessment of Object Use for Task Modeling.	TAMODIA/HCSE	2008	DBLP DOI BibTeX RDF	K-MADe, evaluation, objects, task models
1	Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin	An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing.	VTS	2008	DBLP DOI BibTeX RDF	write driver, design-for-diagnosis, diagnosis, SRAM
1	Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin	A Design-for-Diagnosis Technique for SRAM Write Drivers.	DATE	2008	DBLP DOI BibTeX RDF
1	Dimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen	Power-Aware Testing and Test Strategies for Low Power Devices.	DATE	2008	DBLP DOI BibTeX RDF
1	Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Using TMR Architectures for Yield Improvement.	DFT	2008	DBLP DOI BibTeX RDF
1	Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi	SoC Symbolic Simulation: a case study on delay fault testing.	DDECS	2008	DBLP DOI BibTeX RDF
1	Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Yield Improvement, Fault-Tolerance to the Rescue?.	IOLTS	2008	DBLP DOI BibTeX RDF
1	Patrick Girard, Vincent Thomson	Energy Model based Control for Forming Processes.	ICINCO-ICSO	2008	DBLP BibTeX RDF
1	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	Resistive-open defects, Pre-charge circuits, Memory testing, Dynamic faults
1	Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Jean Michel Daga	A concurrent approach for testing address decoder faults in eFlash memories.	ITC	2007	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, Laung-Terng Wang	A novel scheme to reduce power supply noise for high-quality at-speed scan testing.	ITC	2007	DBLP DOI BibTeX RDF
1	Sybille Caffiau, Patrick Girard, Dominique L. Scapin, Laurent Guittet	Generating Interactive Applications from Task Models: A Hard Challenge.	TAMODIA	2007	DBLP DOI BibTeX RDF	generation, Task models
1	Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	DERRIC: A Tool for Unified Logic Diagnosis.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window.	VTS	2007	DBLP DOI BibTeX RDF
1	Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs.	VTS	2007	DBLP DOI BibTeX RDF
1	Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Slow write driver faults in 65nm SRAM technology: analysis and March test solution.	DATE	2007	DBLP DOI BibTeX RDF
1	Patrick Girard, Andrzej Krasniewski, Elena Gramatová, Adam Pawlak, Tomasz Garbolino (eds.)	Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007	DDECS	2007	DBLP BibTeX RDF
1	Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	A Mixed Approach for Unified Logic Diagnosis.	DDECS	2007	DBLP BibTeX RDF
1	Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard	Reducing Power Dissipation in SRAM during Test.	J. Low Power Electronics	2006	DBLP DOI BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	A Gated Clock Scheme for Low Power Testing of Logic Cores.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	test-per-scan, test-per-clock, low power design, low power test
1	Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	BIST, delay faults, look-up table
1	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan	ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	address decoders, memory testing, dynamic faults
1	Zahir Albadawi, Benoit Boulet, Robert DiRaddo, Patrick Girard, Alexandre Rail, Vincent Thomson	Agent-based control of manufacturing processes.	IJMR	2006	DBLP DOI BibTeX RDF
1	Loé Sanou, Patrick Girard, Laurent Guittet	Comparaison de deux méthodes pour implémenter la programmation sur exemple.	IHM	2006	DBLP DOI BibTeX RDF	swing events, human computer interaction, toolkit, programming by demonstration
1	Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich	Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Olivier Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	An Overview of Failure Mechanisms in Embedded Flash Memories.	VTS	2006	DBLP DOI BibTeX RDF
1	Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard	Minimizing test power in SRAM through reduction of pre-charge activity.	DATE	2006	DBLP DOI BibTeX RDF
1	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit.	DDECS	2006	DBLP BibTeX RDF
1	Patrick Girard	Welcome to the Journal of Low Power Electronics.	J. Low Power Electronics	2005	DBLP DOI BibTeX RDF
1	Patrick Girard, Yannick Bonhomme	Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing.	J. Low Power Electronics	2005	DBLP DOI BibTeX RDF
1	Simone Borri, Magali Bastian Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel	Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	address decoders, core-cells, memory testing, dynamic faults
1	Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	look-up table (LUT), FPGA, test, delay fault
1	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan	Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	SRAM core-cell, resistive open defects, memory testing, March test, dynamic faults
1	Nicolas Guibert, Laurent Guittet, Patrick Girard	Validation d'une approche " basée sur exemples " pour l'apprentissage de la programmation.	IHM	2005	DBLP DOI BibTeX RDF	computer-aided learning & teaching, psychology & didactics of programming, experimentations, programming by demonstration
1	Nabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault	Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives.	PATMOS	2005	DBLP DOI BibTeX RDF
1	Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault	Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
1	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies.	DAC	2005	DBLP DOI BibTeX RDF	SRAM memories, VDSM technologies, core-cell, test, march test, dynamic faults, defect analysis
1	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan	Data Retention Fault in SRAM Memories: Analysis and Detection Procedures.	VTS	2005	DBLP DOI BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	Power-Driven Routing-Constrained Scan Chain Design.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	scan chain design, DfT, low power testing, scan testing
1	Benoit Boulet, Robert DiRaddo, Patrick Girard, Vincent Thomson	An agent based architecture for model based control.	SMC	2004	DBLP DOI BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Design of Routing-Constrained Low Power Scan Chains.	DELTA	2004	DBLP DOI BibTeX RDF
1	Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	High Quality TPG for Delay Faults in Look-Up Tables of FPGAs.	DELTA	2004	DBLP DOI BibTeX RDF

Publications of "Patrick Girard" ( http://dblp.L3S.de/Authors/Patrick_Girard )