| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Per Stenström, Koen De Bosschere |
Introduction to the special issue on high-performance and embedded architectures and compilers.  |
TACO  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström |
π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory. |
HPCA |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Per Stenström (eds.) |
Transactions on High-Performance Embedded Architectures and Compilers III |
T. HiPEAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Per Stenström (eds.) |
Transactions on High-Performance Embedded Architectures and Compilers IV |
T. HiPEAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Anurag Negi, Per Stenström, J. Rubén Titos Gil, Manuel E. Acacio, José M. García |
Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory. |
PACT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström |
The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems. |
IPDPS Workshops |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Per Stenström, Doug Burger, Wen-mei W. Hwu, Vipin Kumar, Kunle Olukotun, David A. Padua, Burton Smith |
Panel Statement. |
IPDPS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Madhavan Manivannan, Ben H. H. Juurlink, Per Stenström |
Implications of Merging Phases on Scalability of Multi-core Architectures. |
ICPP |
2011 |
DBLP DOI BibTeX RDF |
Redcution operations, Chip Multiprocessor, Amdahl's Law |
| 1 | Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström |
Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory. |
ICPP |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mafijul Md. Islam, Per Stenström |
A unified approach to eliminate memory accesses early. |
CASES |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström |
ZEBRA: a data-centric, hybrid-policy hardware transactional memory design. |
ICS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Madhavan Manivannan, Ben H. H. Juurlink, Per Stenström |
Poster: implications of merging phases on scalability of multi-core architectures. |
ICS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yehuda Afek, Ulrich Drepper, Pascal Felber, Christof Fetzer, Vincent Gramoli, Michael Hohmuth, Etienne Riviere, Per Stenström, Osman S. Unsal, Walther Maldonado, Derin Harmanci, Patrick Marlier, Stephan Diestelhorst, Martin Pohlack, Adrián Cristal, Ibrahim Hur, Aleksandar Dragojevic, Rachid Guerraoui, Michal Kapalka, Sasa Tomic, Guy Korland, Nir Shavit, Martin Nowack, Torvald Riegel |
The Velox Transactional Memory Stack. |
IEEE Micro |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Anurag Negi, M. M. Waliullah, Per Stenström |
LV*: A low complexity lazy versioning HTM infrastructure. |
ICSAMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mafijul Md. Islam, Per Stenström |
Characterization and exploitation of narrow-width loads: the narrow-width cache approach. |
CASES |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | M. M. Waliullah, Per Stenström |
Schemes for avoiding starvation in transactional memory systems. |
Concurrency and Computation: Practice and Experience |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Per Stenström, David B. Whalley |
Introduction. |
T. HiPEAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Per Stenström (eds.) |
Transactions on High-Performance Embedded Architectures and Compilers II |
T. HiPEAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström |
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. |
Signal Processing Systems |
2009 |
DBLP DOI BibTeX RDF |
Reconfigurable, Computer architecture, Interconnect, Flexible |
| 1 | Md. Mafijul Islam, Per Stenström |
Zero-Value Caches: Cancelling Loads that Return Zero. |
PACT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Md. Mafijul Islam, Sally A. McKee, Per Stenström |
Cancellation of loads that return zero using zero-value caches. |
ICS |
2009 |
DBLP DOI BibTeX RDF |
frequent value locality, load criticality, zero load, cache |
| 1 | Martin Thuresson, Magnus Själander, Per Stenström |
A Flexible Code Compression Scheme Using Partitioned Look-Up Tables. |
HiPEAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jochen Hollmann, Per Stenström |
Using Hoarding to Increase Availability in Shared File Systems. |
ACIS-ICIS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Md. Mafijul Islam, Magnus Själander, Per Stenström |
Early detection and bypassing of trivial operations to improve energy efficiency of processors. |
Microprocessors and Microsystems - Embedded Hardware Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Fredrik Warg, Per Stenström |
Dual-thread Speculation: A Simple Approach to Uncover Thread-level Parallelism on a Simultaneous Multithreaded Processor. |
International Journal of Parallel Programming |
2008 |
DBLP DOI BibTeX RDF |
Computer architecture, Chip multiprocessors, Thread-level speculation, Thread-level parallelism, Simultaneous multithreading |
| 1 | Reinhard Wilhelm, Jakob Engblom, Andreas Ermedahl, Niklas Holsti, Stephan Thesing, David B. Whalley, Guillem Bernat, Christian Ferdinand, Reinhold Heckmann, Tulika Mitra, Frank Mueller, Isabelle Puaut, Peter P. Puschner, Jan Staschulat, Per Stenström |
The worst-case execution-time problem - overview of methods and survey of tools. |
ACM Trans. Embedded Comput. Syst. |
2008 |
DBLP DOI BibTeX RDF |
worst-case execution times, Hard real time |
| 1 | Martin Thuresson, Lawrence Spracklen, Per Stenström |
Memory-Link Compression Schemes: A Value Locality Perspective. |
IEEE Trans. Computers |
2008 |
DBLP DOI BibTeX RDF |
Memory Structures, Data compaction and compression, I/O and Data Communications |
| 1 | M. M. Waliullah, Per Stenström |
Efficient management of speculative data in hardware transactional memory systems. |
ICSAMOS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete, Per Stenström |
Leveraging Data Promotion for Low Power D-NUCA Caches. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | M. M. Waliullah, Per Stenström |
Intermediate checkpointing with conflicting access prediction in transactional memory systems. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Martin Thuresson, Per Stenström |
Accommodation of the Bandwidth of Large Cache Blocks Using Cache/Memory Link Compression. |
ICPP |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Per Stenström, Michel Dubois, Manolis Katevenis, Rajiv Gupta, Theo Ungerer (eds.) |
High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings |
HiPEAC |
2008 |
DBLP BibTeX RDF |
|
| 1 | M. M. Waliullah, Per Stenström |
Starvation-free commit arbitration policies for transactional memory systems. |
SIGARCH Computer Architecture News |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Alessandro Bardine, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete, Per Stenström |
Improving power efficiency of D-NUCA caches. |
SIGARCH Computer Architecture News |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Haakon Dybdahl, Per Stenström, Lasse Natvig |
An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches. |
SIGARCH Computer Architecture News |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Per Stenström |
Introduction to Part 1. |
T. HiPEAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Koen De Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Michael F. P. O'Boyle, Dionisios N. Pnevmatikatos, Alex Ramírez, Pascal Sainrat, André Seznec, Per Stenström, Olivier Temam |
High-Performance Embedded Architecture and Compilation Roadmap. |
T. HiPEAC |
2007 |
DBLP DOI BibTeX RDF |
HiPEAC, single core architecture, programming models and tools, simulation and system modelling, real-time systems, compilation, interconnection networks, benchmarking, reconfigurable computing, run-time systems, multi-core architecture, roadmap |
| 1 | Per Stenström, Michael F. P. O'Boyle, François Bodin, Marcelo Cintra, Sally A. McKee (eds.) |
Transactions on High-Performance Embedded Architectures and Compilers I |
T. HiPEAC |
2007 |
DBLP BibTeX RDF |
|
| 1 | Jianwei Chen, Michel Dubois, Per Stenström |
SimWattch: Integrating Complete-System and User-Level Performance and Power Simulators. |
IEEE Micro |
2007 |
DBLP DOI BibTeX RDF |
simulation, low-power design, power management, modeling of computer architecture |
| 1 | Jochen Hollmann, Anders Ardö, Per Stenström |
Effectiveness of caching in a distributed digital library system. |
Journal of Systems Architecture |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström |
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. |
ICSAMOS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | M. M. Waliullah, Per Stenström |
Starvation-Free Transactional Memory-System Protocols. |
Euro-Par |
2007 |
DBLP DOI BibTeX RDF |
Multiprocessors, transactional memory, starvation |
| 1 | Per Stenström |
IPDPS Panel: Is the Multi-Core Roadmap going to Live Up to its Promises? |
IPDPS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Marco Galluzzi, Enrique Vallejo, Adrián Cristal, Fernando Vallejo, Ramón Beivide, Per Stenström, James E. Smith, Mateo Valero |
Implicit Transactional Memory in Kilo-Instruction Multiprocessors. |
Asia-Pacific Computer Systems Architecture Conference |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Md. Mafijul Islam, Alexander Busck, Mikael Engbom, Simji Lee, Michel Dubois, Per Stenström |
Loop-level Speculative Parallelism in Embedded Applications. |
ICPP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Utpal Banerjee, José Moreira, Michel Dubois, Per Stenström (eds.) |
Proceedings of the 4th Conference on Computing Frontiers, 2007, Ischia, Italy, May 7-9, 2007 |
Conf. Computing Frontiers |
2007 |
DBLP BibTeX RDF |
|
| 1 | Md. Mafijul Islam, Per Stenström |
Energy and Performance Trade-offs between Instruction Reuse and Trivial Computations for Embedded Applications. |
SIES |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Shekhar Borkar, Norman P. Jouppi, Per Stenström |
Microprocessors in the era of terascale integration. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Haakon Dybdahl, Per Stenström |
An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors. |
HPCA |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Koen De Bosschere, David R. Kaeli, Per Stenström, David B. Whalley, Theo Ungerer (eds.) |
High Performance Embedded Architectures and Compilers, Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings |
HiPEAC |
2007 |
DBLP BibTeX RDF |
|
| 1 | Burkhard Monien, Guang Gao, Horst Simon, Paul G. Spirakis, Per Stenström |
Introduction. |
J. Parallel Distrib. Comput. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Md. Mafijul Islam, Per Stenström |
Reduction of Energy Consumption in Processors by Early Detection and Bypassing of Trivial Operations. |
ICSAMOS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Haakon Dybdahl, Per Stenström, Lasse Natvig |
A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors. |
HiPC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Haakon Dybdahl, Per Stenström |
Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination. |
Asia-Pacific Computer Systems Architecture Conference |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaeheon Jeong, Per Stenström, Michel Dubois |
Simple penalty-sensitive replacement policies for caches. |
Conf. Computing Frontiers |
2006 |
DBLP DOI BibTeX RDF |
cache, memory system, replacement policy, penalty |
| 1 | Fredrik Warg, Per Stenström |
Dual-Thread Speculation: Two Threads in the Machine are Worth Eight in the Bush. |
SBAC-PAD |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Martin Thuresson, Per Stenström |
Scalable Value-Cache Based Compression Schemes for Multiprocessors. |
SBAC-PAD |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Per Stenström |
Chip-multiprocessing and beyond. |
HPCA |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Frank Mueller, Per Stenström |
Introduction to the special issue. |
ACM Trans. Embedded Comput. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Magnus Ekman, Per Stenström |
A Robust Main-Memory Compression Scheme. |
ISCA |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Magnus Ekman, Per Stenström |
Enhancing Multiprocessor Architecture Simulation Speed Using Matched-Pair Comparison. |
ISPASS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Magnus Ekman, Per Stenström |
A Cost-Effective Main Memory Organization for Future Servers. |
IPDPS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Fredrik Warg, Per Stenström |
Reducing misspeculation overhead for module-level speculative execution. |
Conf. Computing Frontiers |
2005 |
DBLP DOI BibTeX RDF |
misspeculation prediction, module-level parallelism, performance evaluation, chip multiprocessors, thread-level speculation |
| 1 | Martin Thuresson, Per Stenström |
Evaluation of extended dictionary-based static code compression schemes. |
Conf. Computing Frontiers |
2005 |
DBLP DOI BibTeX RDF |
dynamic decompression, memory size reduction, code compression, code size reduction |
| 1 | Per Stenström |
The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges. |
HiPEAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jonas Jalminger, Per Stenström |
A cache block reuse prediction scheme. |
Microprocessors and Microsystems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Håkan Grahn, Per Stenström |
A comparative evaluation of hardware-only and software-only directory protocols in shared-memory multiprocessors. |
Journal of Systems Architecture |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Martin Kämpe, Per Stenström, Michel Dubois |
Self-correcting LRU replacement policies. |
Conf. Computing Frontiers |
2004 |
DBLP DOI BibTeX RDF |
LRU algorithms, mistake prediction, shadow directories |
| 1 | Magnus Ekman, Per Stenström |
A case for multi-level main memory. |
WMPI |
2004 |
DBLP DOI BibTeX RDF |
memory-systems |
| 1 | Per Stenström |
One Chip, One Server: How Do We Exploit Its Power? |
HiPC |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianwei Chen, Michel Dubois, Per Stenström |
Integrating complete-system and user-level performance/power simulators: the SimWattch approach. |
ISPASS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Fredrik Warg, Per Stenström |
Improving Speculative Thread-Level Parallelism Through Module Run-Length Prediction. |
IPDPS |
2003 |
DBLP DOI BibTeX RDF |
module-level parallelism, module run-length prediction, performance evaluation, Multiprocessors, thread-level speculation |
| 1 | Peter Rundberg, Per Stenström |
Speculative Lock Reordering: Optimistic Out-of-Order Execution of Critical Sections. |
IPDPS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jim Nilsson, Anders Landin, Per Stenström |
The Coherence Predictor Cache: A Resource-Efficient and Accurate Coherence Prediction Infrastructure. |
IPDPS |
2003 |
DBLP DOI BibTeX RDF |
coherence message prediction, memory overhead, caches, Shared-memory multiprocessors |
| 1 | Jonas Jalminger, Per Stenström |
A Novel Approach to Cache Block Reuse Predictions. |
ICPP |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Magnus Ekman, Per Stenström |
Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores. |
ICPP |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jochen Hollmann, Anders Ardö, Per Stenström |
An Evaluation of Document Prefetching in a Distributed Digital Library. |
ECDL |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jonas Jalminger, Per Stenström |
Improvement of energy-efficiency in off-chip caches by selective prefetching. |
Microprocessors and Microsystems |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Magnus Ekman, Per Stenström, Fredrik Dahlgren |
TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
virtual caches, low-power, CMP, snoop |
| 1 | Jochen Hollmann, Anders Ardö, Per Stenström |
Empirical Observations Regarding Predictability in User Access-Behavior in a Distributed Digital Library System. (PDF / PS) |
IPDPS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Martin Kämpe, Per Stenström, Michel Dubois |
The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches. |
HPCA |
2002 |
DBLP DOI BibTeX RDF |
Discrete Fourier Transform, Branch Prediction, Dynamically Scheduled Processors |
| 1 | Peter Rundberg, Per Stenström |
An All-Software Thread-Level Data Dependence Speculation System for Multiprocessors. |
J. Instruction-Level Parallelism |
2001 |
DBLP BibTeX RDF |
|
| 1 | Ulf Assarsson, Per Stenström |
A Case Study of Load Distribution in Parallel View Frustum Culling and Collision Detection. |
Euro-Par |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Per Stenström (eds.) |
Proceedings of the 28th Annual International Symposium on Computer Architecture, ISCA 2001, Göteborg, Sweden, June 30-July 4, 2001 |
ISCA |
2001 |
DBLP BibTeX RDF |
|
| 1 | Fredrik Warg, Per Stenström |
Limits on Speculative Module-Level Parallelism in Imperative and Object-Oriented Programs on CMP Platforms. |
IEEE PACT |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Håkan Grahn, Per Stenström |
Comparative Evaluation of Latency-Tolerating and -Reducing Techniques for Hardware-Only and Software-Only Directory Protocols. |
J. Parallel Distrib. Comput. |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Per Stenström, Erik Hagersten, David J. Lilja, Margaret Martonosi, Madan Venugopal |
Shared-memory multiprocessing: Current state and future directions. |
Advances in Computers |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Silvia M. Müller, Per Stenström, Mateo Valero, Stamatis Vassiliadis |
Parallel Computer Architecture. |
Euro-Par |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashley Saulsbury, Fredrik Dahlgren, Per Stenström |
Recency-based TLB preloading. |
ISCA |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Magnus Karlsson, Fredrik Dahlgren, Per Stenström |
A Prefetching Technique for Irregular Accesses to Linked Data Structures. |
HPCA |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Magnus Karlsson, Per Stenström |
An analytical model of the working-set sizes in decision-support systems. |
SIGMETRICS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Jonas Skeppstedt, Fredrik Dahlgren, Per Stenström |
Evaluation of Compiler-Controlled Updating to Reduce Coherence-Miss Penalties in Shared-Memory Multiprocessors. |
J. Parallel Distrib. Comput. |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas Lundqvist, Per Stenström |
An Integrated Path and Timing Analysis Method based on Cycle-Level Symbolic Execution. |
Real-Time Systems |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas Lundqvist, Per Stenström |
A Method to Improve the Estimated Worst-Case Performance of Data Caching. |
RTCSA |
1999 |
DBLP DOI BibTeX RDF |
predictable data structure, Real-time systems, timing analysis, worst-case execution time, cache analysis |
| 1 | Thomas Lundqvist, Per Stenström |
Timing Anomalies in Dynamically Scheduled Microprocessors. (PDF / PS) |
IEEE Real-Time Systems Symposium |
1999 |
DBLP DOI BibTeX RDF |
timing anomaly, Real-time systems, resource allocation, timing analysis, worst-case execution time, out-of-order execution, dynamically scheduled processor |
| 1 | Fredrik Dahlgren, Michel Dubois, Per Stenström |
Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors. |
IEEE Trans. Computers |
1998 |
DBLP DOI BibTeX RDF |
competitive-update protocols, write caches, performance evaluation, prefetching, Shared-memory multiprocessors, cache-coherence protocols |
| 1 | Thomas Lundqvist, Per Stenström |
Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques. |
LCTES |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Magnus Karlsson, Per Stenström |
Effectivness of Dynamic Prefetching in Multiple-Writer Distributed Virtual Shared-Memory Systems. |
J. Parallel Distrib. Comput. |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Fredrik Dahlgren, Per Stenström, Mårten Björkman |
Reducing the Read-Miss Penalty for Flat COMA Protocols. |
Comput. J. |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Per Stenström, Mats Brorsson, Fredrik Dahlgren, Håkan Grahn, Michel Dubois |
Boosting the Performance of Shared Memory Multiprocessors. |
IEEE Computer |
1997 |
DBLP DOI BibTeX RDF |
|
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