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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 23 occurrences of 21 keywords
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Results
Found 16 publication records. Showing 16 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Gautham N. Chinya, Jamison D. Collins, Perry H. Wang, Hong Jiang, Guei-Yuan Lueh, Thomas Piazza, Hong Wang 0003 |
Bothnia: a dual-personality extension to the Intel integrated graphics driver.  |
Operating Systems Review  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang 0003 |
Intel nehalem processor core made FPGA synthesizable.  |
FPGA  |
2010 |
DBLP DOI BibTeX RDF |
intel nehalem, synthesizable core, fpga, emulator |
| 1 | Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang 0003 |
IntelĀ® atomTM processor core made FPGA-synthesizable.  |
FPGA  |
2009 |
DBLP DOI BibTeX RDF |
intel atom, synthesizable core, fpga, emulator |
| 1 | Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham N. Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang 0003 |
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor.  |
PACT  |
2008 |
DBLP DOI BibTeX RDF |
ia32, on-chip integration, chip multiprocessor, heterogeneous |
| 1 | Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Hong Jiang, Xinmin Tian, Milind Girkar, Nick Y. Yang, Guei-Yuan Lueh, Hong Wang 0003 |
EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system.  |
PLDI  |
2007 |
DBLP DOI BibTeX RDF |
GPU, openMP, heterogeneous multi-cores |
| 1 | Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Bernard Lint, Asit Mallick, Koichi Yamada, Hong Wang 0003 |
Sequencer virtualization.  |
ICS  |
2007 |
DBLP DOI BibTeX RDF |
virtualization, multi-cores, MIMD |
| 1 | Richard A. Hankins, Gautham N. Chinya, Jamison D. Collins, Perry H. Wang, Ryan Rakvic, Hong Wang 0003, John Paul Shen |
Multiple Instruction Stream Processor.  |
ISCA  |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Satish Narayanasamy, Hong Wang 0003, Perry H. Wang, John Paul Shen, Brad Calder |
A Dependency Chain Clustered Microarchitecture.  |
IPDPS  |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Perry H. Wang, Jamison D. Collins, Hong Wang 0003, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen |
Helper Threads via Virtual Multithreading.  |
IEEE Micro  |
2004 |
DBLP DOI BibTeX RDF |
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| 1 | Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan del Cuvillo, Xinmin Tian, Xiang Zou, Hong Wang 0003, Donald Yeung, Milind Girkar, John Paul Shen |
Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors.  |
CGO  |
2004 |
DBLP DOI BibTeX RDF |
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| 1 | Perry H. Wang, Jamison D. Collins, Hong Wang 0003, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen |
Helper threads via virtual multithreading on an experimental itaniumĀ® 2 processor-based platform.  |
ASPLOS  |
2004 |
DBLP DOI BibTeX RDF |
DB2 database, cache miss prefetching, itanium processor, switch-on-event, multithreading, helper thread, PAL |
| 1 | Hong Wang 0003, Shiri Manor, Dave LaFollette, Nadav Nesher, Ku-jei King, Perry H. Wang, Shay Levy, Shai Satt, Gal Carmeli, Arjun Kapur, Ioannis Schoinas, Ed Rubinstein, Rahul Bhatt |
Inferno: a functional simulation infrastructure for modeling microarchitectural data speculations.  |
ISPASS  |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Shih-Wei Liao, Perry H. Wang, Hong Wang 0003, John Paul Shen, Gerolf Hoflehner, Daniel M. Lavery |
Post-Pass Binary Adaptation for Software-Based Speculative Precomputation.  |
PLDI  |
2002 |
DBLP DOI BibTeX RDF |
chaining speculative precomputation, dependence reduction, long-range thread-based prefetching, loop rotation, post-pass, scheduling, prediction, slicing, speculation, triggering, pointer, slack, delay minimization |
| 1 | R. David Weldon, Steven S. Chang, Hong Wang 0003, Gerolf Hoflehner, Perry H. Wang, Daniel M. Lavery, John Paul Shen |
Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors.  |
Interaction between Compilers and Computer Architectures  |
2002 |
DBLP DOI BibTeX RDF |
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| 1 | Perry H. Wang, Hong Wang 0003, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Paul Shen |
Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation.  |
HPCA  |
2002 |
DBLP DOI BibTeX RDF |
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| 1 | Perry H. Wang, Hong Wang 0003, Ralph-Michael Kling, Kalpana Ramakrishnan, John Paul Shen |
Register Renaming and Scheduling for Dynamic Execution of Predicated Code.  |
HPCA  |
2001 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #16 of 16 (100 per page; Change: )
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