| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes |
A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors.  |
T. HiPEAC  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung |
Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization. |
Comput. J. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung |
Blur identification with assumption validation for sensor-based video reconstruction and its implementation on field programmable gate array. |
IET Computers & Digital Techniques |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter Y. K. Cheung |
Introduction to special section FPGA 2009. |
TRETS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Edward A. Stott, Peter Y. K. Cheung |
Improving FPGA Reliability with Wear-Levelling. |
FPL |
2011 |
DBLP DOI BibTeX RDF |
FPGA, Reliability, NBTI, Degradation, Wear Levelling |
| 1 | Sumanta Chaudhuri, Justin S. Wong, Peter Y. K. Cheung |
Timing speculation in FPGAs: Probabilistic inference of data dependent failure rates. |
FPT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung |
Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Justin S. Wong, Peter Y. K. Cheung |
Improved delay measurement method in FPGA based on transition probability. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter Jamieson, Tobias Becker, Peter Y. K. Cheung, Wayne Luk, Tero Rissa, Teemu Pitkänen |
Benchmarking and evaluating reconfigurable architectures targeting the mobile domain. |
ACM Trans. Design Autom. Electr. Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes |
Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study. |
IEEE Trans. Computers |
2010 |
DBLP DOI BibTeX RDF |
video, performance measures, reconfigurable hardware, Graphics processors, real-time and embedded systems, signal processing systems |
| 1 | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
FPGA Architecture Optimization Using Geometric Programming. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa |
Power Characterisation for Fine-Grain Reconfigurable Fabrics. |
Int. J. Reconfig. Comp. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung |
Fault tolerance and reliability in field-programmable gate arrays. |
IET Computers & Digital Techniques |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Christos-Savvas Bouganis, Iosifina Pournara, Peter Y. K. Cheung |
Exploration of Heterogeneous FPGAs for Mapping Linear Projection Designs. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Asma Kahoul, Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods. |
TRETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays. |
TRETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk |
Wave-pipelined intra-chip signaling for on-FPGA communications. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Edward A. Stott, Justin S. Wong, Peter Y. K. Cheung |
Degradation Analysis and Mitigation in FPGAs. |
FPL |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | David Huw Jones, Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung |
GPU Versus FPGA for High Productivity Computing. |
FPL |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | David Huw Jones, Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung |
A Salient Region Detector for GPU Using a Cellular Automata Architecture. |
ICONIP |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tobias Becker, Wayne Luk, Peter Y. K. Cheung |
Energy-Aware Optimisation for Run-Time Reconfiguration. |
FCCM |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter Y. K. Cheung, John Wawrzynek (eds.) |
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010 |
FPGA |
2010 |
DBLP BibTeX RDF |
|
| 1 | Edward A. Stott, Justin S. Wong, N. Pete Sedcole, Peter Y. K. Cheung |
Degradation in FPGAs: measurement and modelling. |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
FPGA, self test |
| 1 | Sebastián López, Roberto Sarmiento, Philip G. Potter, Wayne Luk, Peter Y. K. Cheung |
Exploration of hardware sharing for image encoders. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Peter Y. K. Cheung |
Process Variability and Degradation: New Frontier for Reconfigurable. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung |
Word-length selection for power minimization via nonlinear optimization. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
word length, synthesis, signal processing, Power consumption, power consumption, bitwidth |
| 1 | Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung |
Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung |
Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems. |
IET Computers & Digital Techniques |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk |
High-throughput one-dimensional median and weighted median filters on FPGA. |
IET Computers & Digital Techniques |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung |
Hardware architectures for eigenvalue computation of real symmetric matrices. |
IET Computers & Digital Techniques |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Christos-Savvas Bouganis, Sung-Boem Park, George A. Constantinides, Peter Y. K. Cheung |
Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs. |
TRETS |
2009 |
DBLP DOI BibTeX RDF |
2D filter design, FPGA, Singular Value Decomposition, reconfigurable logic |
| 1 | Justin S. Wong, N. Pete Sedcole, Peter Y. K. Cheung |
Self-Measurement of Combinatorial Circuit Delays in FPGAs. |
TRETS |
2009 |
DBLP DOI BibTeX RDF |
FPGA, Testing, configuration, delay measurement |
| 1 | Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides |
Robust Real-Time Super-Resolution on FPGA and an Application to Video Enhancement. |
TRETS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | N. Pete Sedcole, Edward A. Stott, Peter Y. K. Cheung |
Compensating for variability in FPGAs by re-mapping and re-placement. |
FPL |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
Area estimation and optimisation of FPGA routing fabrics. |
FPL |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung |
A sensor-based approach to linear blur identification for real-time video enhancement. |
ICIP |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter Jamieson, Tobias Becker, Wayne Luk, Peter Y. K. Cheung, Tero Rissa, Teemu Pitkänen |
Benchmarking Reconfigurable Architectures in the Mobile Domain. |
FCCM |
2009 |
DBLP DOI BibTeX RDF |
Mobile Domain, FPGA, Low Power, Reconfigurable Architectures |
| 1 | Paul Chow, Peter Y. K. Cheung (eds.) |
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009 |
FPGA |
2009 |
DBLP BibTeX RDF |
|
| 1 | Philip G. Potter, Wayne Luk, Peter Y. K. Cheung |
Partition-based exploration for reconfigurable JPEG designs. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Li Wang, Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung |
Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Asma Kahoul, George A. Constantinides, Alastair M. Smith, Peter Y. K. Cheung |
Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep. |
ARC |
2009 |
DBLP DOI BibTeX RDF |
FPGA, Reconfigurable architectures, Floorplanning, integer linear programming (ILP) |
| 1 | Tobias Becker, Wayne Luk, Peter Y. K. Cheung |
Parametric Design for Reconfigurable Software-Defined Radio. |
ARC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam |
A DP-network for optimal dynamic routing in network-on-chip. |
CODES+ISSS |
2009 |
DBLP DOI BibTeX RDF |
optimal and sub-optimal routing, dynamic programming, network-on-chip, adaptive routing |
| 1 | Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung |
Custom parallel caching schemes for hardware-accelerated image compression. |
J. Real-Time Image Processing |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter Y. K. Cheung, Alexandre Yakovlev |
Comments on the BCS Lecture "The Future of Computer Technology and its Implications for the Computer Industry" by Professor Steve Furber. |
Comput. J. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sutjipto Arifin, Peter Y. K. Cheung |
Affective Level Video Segmentation by Utilizing the Pleasure-Arousal-Dominance Information. |
IEEE Transactions on Multimedia |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kieron Turkington, Turkington A. Constantinides, Kostas Masselos, Peter Y. K. Cheung |
Outer Loop Pipelining for Application Specific Datapaths in FPGAs. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Maria E. Angelopoulou, Kostas Masselos, Peter Y. K. Cheung, Yiannis Andreopoulos |
Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs. |
Signal Processing Systems |
2008 |
DBLP DOI BibTeX RDF |
5/3 lifting filter-pair, row-column, line-based, FPGA, implementation, discrete wavelet transform, comparison, lifting scheme, block-based |
| 1 | N. Pete Sedcole, Peter Y. K. Cheung |
Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations. |
TRETS |
2008 |
DBLP DOI BibTeX RDF |
statistical theory, within-die variability, modeling, FPGA, Delay, reconfiguration, process variation, yield |
| 1 | Ben Cope, Peter Y. K. Cheung, Wayne Luk |
Systematic design space exploration for customisable multi-processor architectures. |
ICSAMOS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa |
Towards benchmarking energy efficiency of reconfigurable architectures. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung |
Fault tolerant methods for reliability in FPGAs. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung |
Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Justin S. Wong, Peter Y. K. Cheung, N. Pete Sedcole |
Combating process variation on FPGAS with a precise at-speed delay measurement method. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung |
Characterisation of FPGA Clock Variability. |
ISVLSI |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung |
Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation. |
BCS Int. Acad. Conf. |
2008 |
DBLP BibTeX RDF |
|
| 1 | Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk |
Implementation of Wave-Pipelined Interconnects in FPGAs. |
NOCS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk |
Interconnection lengths and delays estimation for communication links in FPGAs. |
SLIP |
2008 |
DBLP DOI BibTeX RDF |
communciation link, interconnection length prediction, FPGA |
| 1 | Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk |
Global interconnections in FPGAs: modeling and performance analysis. |
SLIP |
2008 |
DBLP DOI BibTeX RDF |
FPGA, throughput, interconnection, wave-pipelined |
| 1 | Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung |
Video enhancement on an adaptive image sensor. |
ICIP |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk |
High-throughput interconnect wave-pipelining for global communication in FPGAs. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung |
Measuring and modeling FPGA clock variability. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
within-die variability, modeling, FPGA, process variation, clock skew |
| 1 | Ben Cope, Peter Y. K. Cheung, Wayne Luk |
Using Reconfigurable Logic to Optimise GPU Memory Accesses. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung, Alastair M. Smith |
Glitch-aware output switching activity from word-level statistics. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides |
FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor. |
ARC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk |
Real-time hardware acceleration of the trace transform. |
J. Real-Time Image Processing |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung |
ROM to DSP block transfer for resource constrained synthesis. |
IET Computers & Digital Techniques |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk |
Run-Time Integration of Reconfigurable Video Processing Systems. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung |
On the feasibility of early routing capacitance estimation for FPGAs. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung |
Efficient mapping of a Kalman filter into an FPGA using Taylor Expansion. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam |
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. |
NOCS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Sutjipto Arifin, Peter Y. K. Cheung |
A Novel Video Parsing Algorithm Utilizing the Pleasure-Arousal-Dominance Emotional Information. |
ICIP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ben Cope, Peter Y. K. Cheung, Wayne Luk |
Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung |
Automatic On-chip Memory Minimization for Data Reuse. |
FCCM |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Christos-Savvas Bouganis, Iosifina Pournara, Peter Y. K. Cheung |
Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAs. |
FCCM |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung |
A Hybrid Memory Sub-system for Video Coding Applications. |
FCCM |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Tobias Becker, Wayne Luk, Peter Y. K. Cheung |
Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration. |
FCCM |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | N. Pete Sedcole, Peter Y. K. Cheung |
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis. |
FPGA |
2007 |
DBLP DOI BibTeX RDF |
statistical theory, within-die variability, modelling, FPGA, delay, reconfiguration, process variation, yield |
| 1 | Sutjipto Arifin, Peter Y. K. Cheung |
A Novel Probabilistic Approach to Modeling the Pleasure-Arousal-Dominance Content of the Video based on "Working Memory". |
ICSC |
2007 |
DBLP DOI BibTeX RDF |
Affective video content analysis, emotion recognition, Dynamic Bayesian networks |
| 1 | Sutjipto Arifin, Peter Y. K. Cheung |
A computation method for video segmentation utilizing the pleasure-arousal-dominance emotional information. |
ACM Multimedia |
2007 |
DBLP DOI BibTeX RDF |
affective video content analysis, video segmentation |
| 1 | N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk |
On-Chip Communication in Run-Time Assembled Reconfigurable Systems. |
ICSAMOS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko |
Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Christos-Savvas Bouganis, Peter Y. K. Cheung, Zhaoping Li |
FPGA-Accelerated Pre-Attentive Segmentation in Primary Visual Cortex. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk |
Efficient Realtime FPGA Implementation of the Trace Transform. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sutjipto Arifin, Peter Y. K. Cheung |
Towards Affective Level Video Applications: A Novel FPGA-Based Video Arousal Content Modeling System. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk |
On-FPGA Communication Architectures and Design Factors. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sutjipto Arifin, Peter Y. K. Cheung |
User Attention Based Arousal Content Modeling. |
ICIP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung |
A Spatiotemporal Saliency Framework. |
ICIP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design. |
FCCM |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko |
Yield enhancements of design-specific FPGAs. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
design-specific FPGA, interconnect faults, interconnect utilization, yield enhancement, yield prediction, structured ASIC, FPGA interconnect |
| 1 | Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung, Philip Heng Wai Leong, Stephen J. Motley |
Hardware efficient architectures for Eigenvalue computation. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sutjipto Arifin, Peter Y. K. Cheung |
A novel FPGA-based implementation of time adaptive clustering for logical story unit segmentation. |
DATE Designers' Forum |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides, Peter Y. K. Cheung |
Fast word-level power models for synthesis of FPGA-based arithmetic. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Su-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk |
A Flexible Multi-port Caching Scheme for Reconfigurable Platforms. |
ARC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk |
Optimum and heuristic synthesis of multiple word-length architectures. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Ray C. C. Cheung, N. J. Telle, Wayne Luk, Peter Y. K. Cheung |
Customizable elliptic curve cryptosystems. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung |
Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow. |
FPL |
2005 |
DBLP BibTeX RDF |
|
| 1 | Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung |
Power and Area Optimization for Multiple Restricted Multiplication. |
FPL |
2005 |
DBLP BibTeX RDF |
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")