Search results for "Philip Heng Wai Leong"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Gary Chun Tak Chow, Anson Hong Tak Tse, Qiwei Jin, Wayne Luk, Philip Heng Wai Leong, David B. Thomas	A mixed precision Monte Carlo methodology for reconfigurable accelerator systems.	FPGA	2012	DBLP DOI BibTeX RDF
1	Joydip Das, Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk	An Analytical Model Relating FPGA Architecture to Logic Density and Depth.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Haile Yu, Qiang Xu, Philip Heng Wai Leong	On Timing Yield Improvement for FPGA Designs Using Architectural Symmetry.	FPL	2011	DBLP DOI BibTeX RDF	Architectural Symmetry, LE swap, FPGA, Timing Yield
1	Colin Yu Lin, Hayden Kwok-Hay So, Philip Heng Wai Leong	A Model for Matrix Multiplication Performance on FPGAs.	FPL	2011	DBLP DOI BibTeX RDF	technology trend, FPGA, performance model, matrix multiplication
1	Chong H. Ang, Craig T. Jin, Philip Heng Wai Leong, André van Schaik	Spiking neural network-based auto-associative memory using FPGA interconnect delays.	FPT	2011	DBLP DOI BibTeX RDF
1	Colin Yu Lin, Hayden Kwok-Hay So, Philip Heng Wai Leong	A Model for Peak Matrix Performance on FPGAs.	FCCM	2011	DBLP DOI BibTeX RDF
1	Gary Chun Tak Chow, K. W. Kwok, Wayne Luk, Philip Heng Wai Leong	Mixed Precision Processing in Reconfigurable Systems.	FCCM	2011	DBLP DOI BibTeX RDF
1	Jackson H. C. Yeung, Evangeline F. Y. Young, Philip Heng Wai Leong	A monte-carlo floating-point unit for self-validating arithmetic.	FPGA	2011	DBLP DOI BibTeX RDF
1	Haile Yu, Qiang Xu, Philip Heng Wai Leong	On timing yield improvement for FPGA designs using architectural symmetry (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
1	Yuet Ming Lam, José Gabriel F. Coutinho, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk	Multiloop Parallelisation Using Unrolling and Fission.	Int. J. Reconfig. Comp.	2010	DBLP DOI BibTeX RDF
1	Gary Chun Tak Chow, Ken Eguro, Wayne Luk, Philip Heng Wai Leong	A Karatsuba-Based Montgomery Multiplier.	FPL	2010	DBLP DOI BibTeX RDF
1	Haile Yu, Qiang Xu, Philip Heng Wai Leong	Fine-grained characterization of process variation in FPGAs.	FPT	2010	DBLP DOI BibTeX RDF
1	Sam M. H. Ho, Steve C. L. Yuen, Hiu Ching Poon, Thomas C. P. Chau, Yanqing Ai, Philip Heng Wai Leong, Oliver C. S. Choy, Kong-Pang Pun	Structured ASIC: Methodology and comparison.	FPT	2010	DBLP DOI BibTeX RDF
1	Haile Yu, Philip Heng Wai Leong, Qiang Xu	An FPGA chip identification generator using configurable ring oscillator.	FPT	2010	DBLP DOI BibTeX RDF
1	Steve C. L. Yuen, Yanqing Ai, Brian P. W. Chan, Thomas C. P. Chau, Sam M. H. Ho, Oscar K. L. Lau, Kong-Pang Pun, Philip Heng Wai Leong, Oliver C. S. Choy	Rapid prototyping on a structured ASIC fabric.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Thomas C. P. Chau, David W. L. Wu, Yanqing Ai, Brian P. W. Chan, Sam M. H. Ho, Oscar K. L. Lau, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Philip Heng Wai Leong	Design of a single layer programmable Structured ASIC library.	DDECS	2010	DBLP DOI BibTeX RDF
1	Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton	Floating-Point FPGA: Architecture and Modeling.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Joydip Das, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk	Modeling post-techmapping and post-clustering FPGA circuit depth.	FPL	2009	DBLP DOI BibTeX RDF
1	Haile Yu, Philip Heng Wai Leong, Heiko Hinkelmann, Leandro Möller, Manfred Glesner, Peter Zipf	Towards a unique FPGA-based identification circuit using process variations.	FPL	2009	DBLP DOI BibTeX RDF
1	T. Chun Pong Chau, S. Man Ho Ho, Philip Heng Wai Leong, Peter Zipf, Manfred Glesner	Generation of Synthetic Floating-Point benchmark circuits.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H. Ho, Brian P. W. Chan, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Xinan Wang	A comparison of via-programmable gate array logic cell circuits.	FPGA	2009	DBLP DOI BibTeX RDF	logic cell, via-programmable gate arrays
1	Chi Wai Yu, Julien Lamoureux, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk	The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units.	Int. J. Reconfig. Comp.	2008	DBLP DOI BibTeX RDF
1	Jürgen Becker, Michael Hübner, Roger Woods, Philip Heng Wai Leong, Robert Esser, Lionel Torres	Current Trends on Reconfigurable Computing.	Int. J. Reconfig. Comp.	2008	DBLP DOI BibTeX RDF
1	Brian M. H. Li, Philip Heng Wai Leong	Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	FPGA, motion estimation, video compression, bit serial, systolic
1	Steven J. E. Wilton, Chun Hok Ho, Bradley R. Quinton, Philip Heng Wai Leong, Wayne Luk	A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications.	TRETS	2008	DBLP DOI BibTeX RDF	Field programmable gate array, system-on-chip, integrated circuit, silicon debug
1	Yuet Ming Lam, José Gabriel F. Coutinho, Wayne Luk, Philip Heng Wai Leong	Mapping and scheduling with task clustering for heterogeneous computing systems.	FPL	2008	DBLP DOI BibTeX RDF
1	Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton	Rapid estimation of power consumption for hybrid FPGAs.	FPL	2008	DBLP DOI BibTeX RDF
1	Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong	FPGA interconnect design using logical effort.	FPL	2008	DBLP DOI BibTeX RDF
1	Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk	An analytical model describing the relationships between logic architecture and FPGA density.	FPL	2008	DBLP DOI BibTeX RDF
1	Philip Heng Wai Leong	Recent Trends in FPGA Architectures and Applications.	DELTA	2008	DBLP DOI BibTeX RDF	FPGA, applications
1	Jackson H. C. Yeung, C. C. Tsang, Kuen Hung Tsoi, Bill S. H. Kwan, Chris C. C. Cheung, Anthony P. C. Chan, Philip Heng Wai Leong	Map-reduce as a Programming Model for Custom Computing Machines.	FCCM	2008	DBLP DOI BibTeX RDF
1	Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong	FPGA interconnect design using logical effort.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, logical effort
1	Steve C. L. Yuen, Johnny M. H. Lee, Wen J. Li, Philip Heng Wai Leong	An AA-Sized Vibration-Based Microgenerator for Wireless Sensors.	IEEE Pervasive Computing	2007	DBLP DOI BibTeX RDF	micro power generators, self-powered sensors, power electronics, intelligent sensors
1	Philip Heng Wai Leong, Andreas Koch, Eduardo Boemo	Editorial - Field-programmable logic and applications.	IET Computers & Digital Techniques	2007	DBLP DOI BibTeX RDF
1	Kuen Hung Tsoi, K. H. Leung, Philip Heng Wai Leong	High performance physical random number generator.	IET Computers & Digital Techniques	2007	DBLP DOI BibTeX RDF
1	David B. Thomas, Wayne Luk, Philip Heng Wai Leong, John D. Villasenor	Gaussian random number generators.	ACM Comput. Surv.	2007	DBLP DOI BibTeX RDF	simulation, normal, Random numbers, Gaussian
1	Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton	Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications.	FPL	2007	DBLP DOI BibTeX RDF
1	Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton	A synthesizable datapath-oriented embedded FPGA fabric.	FPGA	2007	DBLP DOI BibTeX RDF	embedded block, field programmable gate array, system-on-chip, synthesis, integrated circuit, datapath
1	Dong-U Lee, John D. Villasenor, Wayne Luk, Philip Heng Wai Leong	A Hardware Gaussian Noise Generator Using the Box-Muller Method and Its Error Analysis.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	elementary function approximation, minimax approximation and algorithms, simulation, optimization, field programmable gate arrays, computer arithmetic, error analysis, random number generation, Algorithms implemented in hardware
1	C. K. Wong, Philip Heng Wai Leong	An FPGA-Based Electronic Cochlea with Dual Fixed-Point Arithmetic.	FPL	2006	DBLP DOI BibTeX RDF
1	Kieron Turkington, Konstantinos Masselos, George A. Constantinides, Philip Heng Wai Leong	FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach.	FPL	2006	DBLP DOI BibTeX RDF
1	Guangyi Shi, Cheung-Shing Chan, Yilun Luo, Guanglie Zhang, Wen J. Li, Philip Heng Wai Leong, Kwok-Sui Leung	Development of a Human Airbag System for Fall Protection Using MEMS Motion Sensing Technology.	IROS	2006	DBLP DOI BibTeX RDF
1	Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, Sergio López-Buedo	Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs.	FCCM	2006	DBLP DOI BibTeX RDF
1	Chi Chiu Tsang, Gary Chun Tak Chow, Philip Heng Wai Leong, Guanglie Zhang, Yilun Luo, Zhuxin Dong, Guangyi Shi, Sze Yin Kwok, Heidi Y. Y. Wong, Wen J. Li, Ming Yiu Wong	A Novel Real-Time Error Compensation Methodology for ?IMU-based Digital Writing Instrument.	ROBIO	2006	DBLP DOI BibTeX RDF
1	Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung, Philip Heng Wai Leong, Stephen J. Motley	Hardware efficient architectures for Eigenvalue computation.	DATE	2006	DBLP DOI BibTeX RDF
1	Ocean Y. H. Cheung, Philip Heng Wai Leong, Eric K. C. Tsang, Bertram Emil Shi	A Scalable FPGA Implementation of Cellular Neural Networks for Gabor-type Filtering.	IJCNN	2006	DBLP DOI BibTeX RDF
1	Monk-Ping Leong, Chi Chiu Cheung, Chin-Wang Cheung, Polly P. M. Wan, Ivan K. H. Leung, Winnie M. M. Yeung, Wing Seung Yuen, Kenneth S. K. Chow, Kwong-Sak Leung, Philip Heng Wai Leong	CPE: A Parallel Library for Financial Engineering Applications.	IEEE Computer	2005	DBLP DOI BibTeX RDF	Clustertech parallel environment, Financial engineering, CPE architecture, Finite-difference calculation, Parallel computing, Monte Carlo simulation
1	Dong-U Lee, Wayne Luk, John D. Villasenor, Guanglie Zhang, Philip Heng Wai Leong	A hardware Gaussian noise generator using the Wallace method.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Tero Rissa, Steven J. E. Wilton, Philip Heng Wai Leong (eds.)	Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005	FPL	2005	DBLP BibTeX RDF
1	Guanglie Zhang, Philip Heng Wai Leong, Dong-U Lee, John D. Villasenor, Ray C. C. Cheung, Wayne Luk	Ziggurat-based Hardware Gaussian Random Number Generator.	FPL	2005	DBLP BibTeX RDF
1	Kuen Hung Tsoi, Philip Heng Wai Leong	Mullet - A Parallel Multiplier Generator.	FPL	2005	DBLP BibTeX RDF
1	Gary Chun Tak Chow, L. S. M. Tsui, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton	Dynamic Voltage Scaling for Commercial FPGAs.	FPT	2005	DBLP BibTeX RDF
1	Ocean Y. H. Cheung, Philip Heng Wai Leong, Eric K. C. Tsang, Bertram Emil Shi	Implementation of Gabor-Type Filters on Field Programmable Gate Arrays.	FPT	2005	DBLP BibTeX RDF
1	Guanglie Zhang, Philip Heng Wai Leong, Chun Hok Ho, Kuen Hung Tsoi, Chris C. C. Cheung, Dong-U Lee, Ray C. C. Cheung, Wayne Luk	Reconfigurable Acceleration for Monte Carlo Based Financial Simulation.	FPT	2005	DBLP BibTeX RDF
1	Johnny M. H. Lee, Steve C. L. Yuen, Mimi H. M. Luk, Gordon M. H. Chan, King Fong Lei, Wen J. Li, Philip Heng Wai Leong, Yeung Yam	Self-Powered Wireless temperature Sensing Using MEMS-Based AA-Size Energy Transducer.	I. J. Information Acquisition	2004	DBLP DOI BibTeX RDF
1	Ralf Ludewig, Oliver Soffke, Peter Zipf, Manfred Glesner, Kong-Pang Pun, Kuen Hung Tsoi, Kin-Hong Lee, Philip Heng Wai Leong	IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter.	FPL	2004	DBLP DOI BibTeX RDF
1	Kuen Hung Tsoi, Chun Hok Ho, H. C. Yeung, Philip Heng Wai Leong	An Arithmetic Library and Its Application to the N-body Problem.	FCCM	2004	DBLP DOI BibTeX RDF
1	Monk-Ping Leong, Craig T. Jin, Philip Heng Wai Leong	An FPGA-Based Electronic Cochlea.	EURASIP J. Adv. Sig. Proc.	2003	DBLP DOI BibTeX RDF
1	Monk-Ping Leong, Philip Heng Wai Leong	A variable-radix digit-serial design methodology and its application to the discrete cosine transform.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Chi Wai Yu, K. H. Kwong, Kin-Hong Lee, Philip Heng Wai Leong	A Smith-Waterman Systolic Cell.	FPL	2003	DBLP DOI BibTeX RDF
1	Stanley Y. C. Li, Gap C. K. Cheuk, Kin-Hong Lee, Philip Heng Wai Leong	FPGA-based SIMD Processor. (PDF / PS)	FCCM	2003	DBLP DOI BibTeX RDF
1	Kuen Hung Tsoi, K. H. Leung, Philip Heng Wai Leong	Compact FPGA-based True and Pseudo Random Number Generators.	FCCM	2003	DBLP DOI BibTeX RDF
1	Johnny M. H. Lee, Steve C. L. Yuen, Wen J. Li, Philip Heng Wai Leong	Development of an AA size energy transducer with micro resonators.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Philip Heng Wai Leong, Ivan K. H. Leung	A microcoded elliptic curve processor using FPGA technology.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Chun Hok Ho, Philip Heng Wai Leong, Kuen Hung Tsoi, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner	Fly - A Modifiable Hardware Compiler.	FPL	2002	DBLP DOI BibTeX RDF
1	Kurt K. Ting, Steve C. L. Yuen, Kin-Hong Lee, Philip Heng Wai Leong	An FPGA Based SHA-256 Processor.	FPL	2002	DBLP DOI BibTeX RDF
1	Chun Hok Ho, Monk-Ping Leong, Philip Heng Wai Leong, Jürgen Becker, Manfred Glesner	Rapid Prototyping of FPGA Based Floating Point DSP Systems.	IEEE International Workshop on Rapid System Prototyping	2002	DBLP DOI BibTeX RDF
1	Kuen Hung Tsoi, Kin-Hong Lee, Philip Heng Wai Leong	A Massively Parallel RC4 Key Search Engine.	FCCM	2002	DBLP DOI BibTeX RDF
1	Philip Heng Wai Leong, C. W. Sham, W. C. Wong, H. Y. Wong, Wing Seung Yuen, Monk-Ping Leong	A bitstream reconfigurable FPGA implementation of the WSAT algorithm.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Ocean Y. H. Cheung, Kuen Hung Tsoi, Philip Heng Wai Leong, Monk-Ping Leong	Tradeoffs in Parallel and Serial Implementations of the International Data Encryption Algorithm IDEA.	CHES	2001	DBLP DOI BibTeX RDF	performance-tradeoffs, reconfigurable-computing, digital-design, Cryptographic hardware
1	Monk-Ping Leong, Ocean Y. H. Cheung, Kuen Hung Tsoi, Philip Heng Wai Leong	A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA.	FCCM	2000	DBLP DOI BibTeX RDF
1	K. H. Leung, K. W. Ma, W. K. Wong, Philip Heng Wai Leong	FPGA Implementation of a Microcoded Elliptic Curve Cryptographic Processor.	FCCM	2000	DBLP DOI BibTeX RDF
1	Wong Hiu Yung, Wing Seung Yuen, Kin-Hong Lee, Philip Heng Wai Leong	A Runtime Reconfigurable Implementation of the GSAT Algorithm.	FPL	1999	DBLP DOI BibTeX RDF
1	Monk-Ping Leong, M. Y. Yeung, C. K. Yeung, C. W. Fu, P. A. Heng, Philip Heng Wai Leong	Automatic Floating to Fixed Point Translation and its Application to Post-Rendering 3D Warping.	FCCM	1999	DBLP DOI BibTeX RDF
1	C. K. Chung, Philip Heng Wai Leong	An Architecture for Solving Boolean Satisfiability Using Runtime Configurable Hardware. (PDF / PS)	ICPP Workshops	1999	DBLP DOI BibTeX RDF
1	T. K. Lee, Philip Heng Wai Leong, K. H. Lee, K. T. Chan, S. K. Hui, H. K. Yeung, M. F. Lo, J. H. M. Lee	An FPGA Implementation of GENET for Solving Graph Coloring Problems .	FCCM	1998	DBLP DOI BibTeX RDF
1	Philip Heng Wai Leong, P. K. Tsang, T. K. Lee	A FPGA Based Forth Microprocessor.	FCCM	1998	DBLP DOI BibTeX RDF
1	Philip Heng Wai Leong, Marwan A. Jabri	Kakadu - A Low Power Analogue Neural Network Classifier.	Int. J. Neural Syst.	1993	DBLP DOI BibTeX RDF

Publications of "Philip Heng Wai Leong" ( http://dblp.L3S.de/Authors/Philip_Heng_Wai_Leong )