Search results for "Placement and Routing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Bjorn De Sutter, Paul Coene, Tom Vander Aa, Bingfeng Mei	Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays.	LCTES	2008	DBLP DOI BibTeX RDF	register allocation, placement and routing, coarse-grained, reconfigurable arrays
3	R. Manimegalai, E. Siva Soumya, V. Muralidharan, Balaraman Ravindran, V. Kamakoti, D. Bhatia	Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines.	VLSI Design	2005	DBLP DOI BibTeX RDF	Three-Dimensional FPGA, Reinforcement Learning (RL), Two-opt algorithm, Support Vector Machines (SVMs), Placement and Routing
3	Miodrag Vujkovic, David Wadkins, William Swartz, Carl Sechen	Efficient timing closure without timing driven placement and routing.	DAC	2004	DBLP DOI BibTeX RDF	digital design flow, gate sizing, placement and routing, timing closure
2	Roozbeh Jafari, Hassan Ghasemzadeh, Foad Dabiri, Ani Nahapetian, Majid Sarrafzadeh	An efficient placement and routing technique for fault-tolerant distributed embedded computing.	ACM Trans. Embedded Comput. Syst.	2009	DBLP DOI BibTeX RDF	fault tolerance, sensor networks, routing, placement, Distributed embedded system
2	Ricardo S. Ferreira, Alex Damiany, Julio C. Goldner Vendramini, Tiago Teixeira, João M. P. Cardoso	On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks.	ARC	2009	DBLP DOI BibTeX RDF
2	Michail Maniatakos, Songhua Xu, Willard L. Miranker	Constraint-Based Placement and Routing for FPGAs Using Self-Organizing Maps.	ICTAI	2008	DBLP DOI BibTeX RDF
2	Devang Jariwala, John Lillis	RBI: Simultaneous Placement and Routing Optimization Technique.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew	SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs.	ISQED	2007	DBLP DOI BibTeX RDF
2	Stefan Raaijmakers, Stephan Wong	Run-time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II-Pro.	FPL	2007	DBLP DOI BibTeX RDF
2	Kostas Siozios, Dimitrios Soudris	A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Min Pan, Chris C. N. Chu	IPR: An Integrated Placement and Routing Algorithm.	DAC	2007	DBLP DOI BibTeX RDF
2	Piotr Stepien, Milan Vasilko	On Feasibility of FPGA Bitstream Compression During Placement and Routing.	FPL	2006	DBLP DOI BibTeX RDF
2	Ning Fu, Mitsutoshi Mineshima, Shigetoshi Nakatake	Multi-SP: A Representation with United Rectangles for Analog Placement and Routing.	ISVLSI	2006	DBLP DOI BibTeX RDF
2	Manuel Rubio del Solar, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido, Miguel A. Vega-Rodríguez	Placement and routing of Boolean functions in constrained FPGAs using a distributed genetic algorithm and local search.	IPDPS	2006	DBLP DOI BibTeX RDF
2	Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar	Placement and Routing in 3D Integrated Circuits.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	VLSI, Placement and routing
2	Roozbeh Jafari, Foad Dabiri, Bo-Kyung Choi, Majid Sarrafzadeh	Efficient placement and routing in grid-based networks.	SAC	2005	DBLP DOI BibTeX RDF	fault-tolerance, sensor networks, routing, placement
2	Young-Su Kwon, Payam Lajevardi, Anantha P. Chandrakasan, Frank Honoré, Donald E. Troxel	A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool.	SLIP	2005	DBLP DOI BibTeX RDF	3-D FPGA, wire resource prediction
2	Roozbeh Jafari, Foad Dabiri, Majid Sarrafzadeh	An Efficient Placement and Routing Technique for Fault-Tolerant Distributed Embedded Computing.	RTCSA	2005	DBLP DOI BibTeX RDF
2	Hui Zhang, Preethi Karthik, Hua Tang, Alex Doboli	An explorative tile-based technique for automated constraint transformation, placement and routing of high frequency analog filters.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Venu G. Gudise, Ganesh K. Venayagamoorthy	FPGA Placement and Routing Using Particle Swarm Optimization.	ISVLSI	2004	DBLP DOI BibTeX RDF
2	Fan Mo, Robert K. Brayton	Fishbone: a block-level placement and routing scheme.	ISPD	2003	DBLP DOI BibTeX RDF	routing, placement
2	Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang	Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing.	SLIP	2003	DBLP DOI BibTeX RDF	?-geometry routing, ?-geometry-driven placement, wirelength reduction estimation
2	Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita	Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts.	VLSI Design	2002	DBLP DOI BibTeX RDF	mixed signal design, shape-based layout, placement, analog design, sequence-pair
2	PariVallal Kannan, Dinesh Bhatia	Tightly Integrated Placement and Routing for FPGAs.	FPL	2001	DBLP DOI BibTeX RDF
2	Chandra Mulpuri, Scott Hauck	Runtime and quality tradeoffs in FPGA placement and routing.	FPGA	2001	DBLP DOI BibTeX RDF	fast CAD for FPGAs, FPGAs, routing, computer-aided design, placement
2	Forrest H. Bennett III, John R. Koza, Jessen Yu, William Mydlowec	Automatic Synthesis, Placement, and Routing of an Amplifier Circuit by Means of Genetic Programming.	ICES	2000	DBLP DOI BibTeX RDF
2	Sree Ganesan, Ranga Vemuri	A Methodology for Rapid Prototyping of Analog Systems.	ICCD	1999	DBLP DOI BibTeX RDF	rapid prototyping, technology mapping, placement and routing, FPAA, field-programmable analog arrays
1	Guanyao Huang, Chia-Wei Chang, Chen-Nee Chuah, Bill Lin	Measurement-Aware Monitor Placement and Routing: A Joint Optimization Approach for Network-Wide Measurements.	IEEE Transactions on Network and Service Management	2012	DBLP DOI BibTeX RDF
1	Joe Wenjie Jiang, Tian Lan, Sangtae Ha, Minghua Chen, Mung Chiang	Joint VM placement and routing for data center traffic engineering.	INFOCOM	2012	DBLP DOI BibTeX RDF
1	Ce Li, Yiping Dong, Takahiro Watanabe	Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Ricardo S. Ferreira, João M. P. Cardoso, Alex Damiany, Julio C. Goldner Vendramini, Tiago Teixeira	Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks.	Journal of Systems Architecture - Embedded Systems Design	2011	DBLP DOI BibTeX RDF
1	Zigang Xiao, Evangeline F. Y. Young	Placement and Routing for Cross-Referencing Digital Microfluidic Biochips.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Yuanteng Pei, Matt W. Mutka	Joint Bandwidth-Aware Relay Placement and Routing in Heterogeneous Wireless Networks.	ICPADS	2011	DBLP DOI BibTeX RDF
1	Keheng Huang, Yu Hu, Xiaowei Li	Cross-layer optimized placement and routing for FPGA soft error mitigation.	DATE	2011	DBLP DOI BibTeX RDF
1	Mohammed A. Abdul-Aziz, Mehdi Baradaran Tahoori	Soft error reliability aware placement and routing for FPGAs.	ITC	2010	DBLP DOI BibTeX RDF
1	Zhangyi Yu, Sanyou Y. Zeng, Yan Guo, Nannan Hu, Liguo Song	Pathfinder Based on Simulated Annealing for Solving Placement and Routing Problem.	ISICA	2010	DBLP DOI BibTeX RDF
1	Linfu Xiao, Evangeline F. Y. Young, Xiaoyong He, K. P. Pun	Practical placement and routing techniques for analog circuit designs.	ICCAD	2010	DBLP DOI BibTeX RDF
1	James Coole, Greg Stitt	Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing.	CODES+ISSS	2010	DBLP DOI BibTeX RDF
1	Pranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta	A novel droplet routing algorithm for digital microfluidic biochips.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	layout, microfluidics, biochips, placement and routing
1	Mihir R. Choudhury, Masoud Rostami, Kartik Mohanram	Dominant critical gate identification for power and yield optimization in logic circuits.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	low-vt, process variations, yield
1	Vassilios Gerousis	Physical design implementation for 3D IC: methodology and tools.	ISPD	2010	DBLP DOI BibTeX RDF	3D IC stack, micro-bump, physical design tools, silicon interposer, methodology, tsv
1	Ataul Bari, Arunita Jaekel, Subir Bandyopadhyay	Optimal placement and routing strategies for resilient two-tiered sensor networks.	Wireless Communications and Mobile Computing	2009	DBLP DOI BibTeX RDF
1	I. Faik Baskaya, David V. Anderson, Sung Kyu Lim	Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing.	IEEE Trans. on Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Weiyi Zhang, Jian Tang, Kendall E. Nygard, Chonggang Wang	REPARE: Regenerator Placement and Routing Establishment in Translucent Networks.	GLOBECOM	2009	DBLP DOI BibTeX RDF
1	Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez	Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing.	ReConFig	2009	DBLP DOI BibTeX RDF	MFPGA, Timing balance, WDDL, Routing, Placement, Differential Power Analysis
1	Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez	Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA.	ICECS	2009	DBLP DOI BibTeX RDF
1	Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly	Transistor-level layout of high-density regular circuits.	ISPD	2009	DBLP DOI BibTeX RDF	transistor layout, placement and routing, regular fabric, dfm
1	Taewook Oh, Bernhard Egger, Hyunchul Park, Scott A. Mahlke	Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures.	LCTES	2009	DBLP DOI BibTeX RDF	software pipelining, placement and routing, coarse-grained reconfigurable architectures
1	Cliff Chiung-Yu Lin, Yao-Wen Chang	ILP-based pin-count aware design methodology for microfluidic biochips.	DAC	2009	DBLP DOI BibTeX RDF	microfludics, design methodology, integer linear programming, biochip
1	Sumanta Chaudhuri	Diagonal tracks in FPGAs: a performance evaluation.	FPGA	2009	DBLP DOI BibTeX RDF	diagonal tracks, octagonal, fpga, hexagonal
1	Chen Dong, Scott Chilstedt, Deming Chen	FPCNA: a field programmable carbon nanotube array.	FPGA	2009	DBLP DOI BibTeX RDF	cnt-based lut, discretized ssta, variation aware cad, fpga, nanoelectronics
1	Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour	Towards automated ECOs in FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	pst, optimization, fpga, boolean satisfiability, resynthesis
1	Kai Wang, Aveek Sarkar, Norman Chang, Shen Lin	Early analysis for power distribution networks.	ISPD	2009	DBLP DOI BibTeX RDF	early analysis, power distribution network
1	Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Rötteler, Niraj K. Jha	A hybrid nano-CMOS architecture for defect and fault tolerance.	JETC	2009	DBLP DOI BibTeX RDF	nanotechnology, Defect tolerance, nanowires
1	Wei Zhang 0012, Niraj K. Jha, Li Shang	A hybrid Nano/CMOS dynamically reconfigurable system - Part II: Design optimization flow.	JETC	2009	DBLP DOI BibTeX RDF	design optimization flow, logic folding, Dynamic reconfiguration, NATURE
1	Ricardo S. Ferreira, Marcone Laure, Antonio Carlos Schneider Beck, Thiago Lo, Mateus B. Rutzig, Luigi Carro	A low cost and adaptable routing network for reconfigurable systems.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Akhilesh Kumar, Mohab Anis	IR-drop management CAD techniques in FPGAs for power grid reliability.	ISQED	2009	DBLP DOI BibTeX RDF
1	Ender Yilmaz, Günhan Dündar	Analog Layout Generator for CMOS Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Kostas Siozios, Dimitrios Soudris	A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs.	J. Low Power Electronics	2008	DBLP DOI BibTeX RDF
1	David Grant, Guy G. Lemieux	Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing.	TRETS	2008	DBLP DOI BibTeX RDF	Automated development tools, hardware-supporting software, testing, graph algorithms, design automation, place and route
1	Bikram Garg, Ashish Agrawal, Rajeev Sehgal, Amarpal Singh, Manish Khanna	Partitioning, floor planning, detailed placement and routing techniques for schematic generation of analog netlist.	EWDTS	2008	DBLP DOI BibTeX RDF
1	Ataul Bari, Yufei Xu, Arunita Jaekel	Integrated Placement and Routing of Relay Nodes for Fault-Tolerant Hierarchical Sensor Networks.	ICCCN	2008	DBLP DOI BibTeX RDF
1	Hyein Lee, Seungwhun Paik, Youngsoo Shin	Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Rajarshi Mukherjee, Song Liu, Seda Ogrenci Memik, Somsubhra Mondal	A high-level clustering algorithm targeting dual Vdd FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	clustering, field programmable gate arrays, partitioning, placement, voltage scaling, Dynamic power
1	Manuel Rubio del Solar, Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez, Antonio Gómez-Iglesias, Miguel Cárdenas Montes	A FPGA Optimization Tool Based on a Multi-island Genetic Algorithm Distributed over Grid Environments.	CCGRID	2008	DBLP DOI BibTeX RDF
1	Igor Loi, Federico Angiolini, Luca Benini	Developing Mesochronous Synchronizers to Enable 3D NoCs.	DATE	2008	DBLP DOI BibTeX RDF
1	Ricardo S. Ferreira, Marcone Laure, Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro	Reducing interconnection cost in coarse-grained dynamic computing through multistage network.	FPL	2008	DBLP DOI BibTeX RDF
1	Justin S. Wong, Peter Y. K. Cheung, N. Pete Sedcole	Combating process variation on FPGAS with a precise at-speed delay measurement method.	FPL	2008	DBLP DOI BibTeX RDF
1	Mohammad Tehranipoor, Reza M. Rad	Defect Tolerance for Nanoscale Crossbar-Based Devices.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF
1	Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Few-Juh Huang, T.-Y. Liu	MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Yan Lin, Lei He, Mike Hutton	Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Kostas Siozios, Dimitrios Soudris	An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs.	PATMOS	2008	DBLP DOI BibTeX RDF	P? CAD Algorithm, FPGA, Management, Power, 3D
1	Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti	A novel approach to the placement and routing problems for field programmable gate arrays.	Appl. Soft Comput.	2007	DBLP DOI BibTeX RDF
1	Tolga Bektas, Osman Oguz, Iradj Ouveysi	A Lagrangean relaxation and decomposition algorithm for the video placement and routing problem.	European Journal of Operational Research	2007	DBLP DOI BibTeX RDF
1	Mohit Pathak, Souvik Mukherjee, Madhavan Swaminathan, Ege Engin, Sung Kyu Lim	Placement and routing of RF embedded passive designs in LCP substrate.	ICCD	2007	DBLP DOI BibTeX RDF
1	Pengyuan Yu, Patrick Schaumont	Secure FPGA circuits using controlled placement and routing.	CODES+ISSS	2007	DBLP DOI BibTeX RDF
1	Mark Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz	Automated generation of layout and control for quantum circuits.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	ion trap, CAD, control, quantum computing, layout
1	Yan Lin, Lei He	Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation.	FPGA	2007	DBLP DOI BibTeX RDF	FPGA, uncertainty, process variation, stochastic, physical synthesis
1	Kai Zhu	Post-route LUT output polarity selection for timing optimization.	FPGA	2007	DBLP DOI BibTeX RDF	optimization, timing, polarity, FPGA lookup table
1	Sachin S. Sapatnekar	Computer-aided design of 3d integrated circuits.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF
1	Lei Cheng, Deming Chen, Martin D. F. Wong, Mike Hutton, Jason Govig	Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Denny Liu	MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs.	DAC	2007	DBLP DOI BibTeX RDF
1	Wei Zhang 0012, Li Shang, Niraj K. Jha	NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture.	DAC	2007	DBLP DOI BibTeX RDF
1	Catherine L. Zhou, Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu	How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs.	DAC	2007	DBLP DOI BibTeX RDF
1	Heinrich Theodor Vierhaus, Helmut Rossmann, Silvio Misera	Timing- / Power-Optimization for Digital Logic Based on Standard Cells.	DSD	2007	DBLP DOI BibTeX RDF
1	Peter M. Athanas, J. Bowen, T. Dunham, Cameron Patterson, J. Rice, Matthew Shelburne, Jorge Surís, Mark B. Bucciero, Jonathan Graf	Wires On Demand: Run-Time Communication Synthesis for Reconfigurable Computing.	FPL	2007	DBLP DOI BibTeX RDF
1	Audip Pandit, Ali Akoglu	Wirelength Prediction for FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
1	Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris	Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support.	FPL	2007	DBLP DOI BibTeX RDF
1	Shuichi Watanabe, Junji Kitamichi, Kenichi Kuroda	A Hardware Algorithm for the Minimum p-Quasi Clique Cover Problem.	FPL	2007	DBLP DOI BibTeX RDF
1	Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew	CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Taraneh Taghavi, Ani Nahapetian, Majid Sarrafzadeh	System Level Estimation of Interconnect Length in the Presence of IP Blocks.	ISQED	2007	DBLP DOI BibTeX RDF	Wirelength Estimation, Hierarchical Placement, Large-scale Circuits, Non-Uniform Probability Distribution, Rent's Rule, IP Blocks
1	Arun Janarthanan, Vijay Swaminathan, Karen A. Tomko	MoCReS: an Area-Efficient Multi-Clock On-Chip Network for Reconfigurable Systems.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Guoqiang Yang, Mei Yang, Yulu Yang, Yingtao Jiang	On the Physicl Layout of PRDT-Based NoCs.	ITNG	2007	DBLP DOI BibTeX RDF
1	Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez	Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances.	NOCS	2007	DBLP DOI BibTeX RDF
1	Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris	A software-supported methodology for designing high-performance 3D FPGA architectures.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Yih-Lang Li, Jin-Yih Li, Wen-Bin Chen	An Efficient Tile-Based ECO Router Using Routing Graph Reduction and Enhanced Global Routing Flow.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Yi-Yu Liu, TingTing Hwang	Crosstalk-Aware Domino-Logic Synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Wei Li, Zibin Dai, Tao Chen, Tao Meng, Xuan Yang	Design and Implementation of a High-Speed Reconfigurable Modular Arithmetic Unit.	APPT	2007	DBLP DOI BibTeX RDF
1	Li Wang, Matthew French, Azadeh Davoodi, Deepak Agarwal	FPGA Dynamic Power Minimization through Placement and Routing Constraints.	EURASIP J. Emb. Sys.	2006	DBLP DOI BibTeX RDF
1	Tolga Bektas, Osman Oguz, Iradj Ouveysi	A novel optimization algorithm for video placement and routing.	IEEE Communications Letters	2006	DBLP DOI BibTeX RDF