Search results for "Power reduction"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao	Dose map and placement co-optimization for timing yield enhancement and leakage power reduction.	DAC	2008	DBLP DOI BibTeX RDF	dose map, placement, timing yield, leakage power reduction
3	Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi	A fast clock scheduling for peak power reduction in LSI.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	general-synchronous framework, peak power reduction, power consumption estimation, clock scheduling
3	Mehrdad Nourani, Mohammad H. Tehranipour	RL-huffman encoding for test compression and power reduction in scan applications.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Huffman encoding, scan applications, scan-in test power, test pattern compression, power reduction, switching activities, test compression, Compression ratio, run-length encoding, decompression
3	Kaveh Shakeri, James D. Meindl	Temperature Variable Supply Voltage for Power Reduction.	ISVLSI	2002	DBLP DOI BibTeX RDF	CMOS, Temperature, Power reduction, Dynamic Power, MOSFET, Static Power
3	Kuen-Jong Lee, Tsung-Chu Huang	An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	multiple scan chains, interleaving scan, test power reduction, peak power reduction
3	Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen	Peak-power reduction for multiple-scan circuits during test application.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	peak-power reduction, multiple scan chain based circuits, peak periodicity, peak width, power waveforms, scan-based circuits, delay buffers, interleaving scan technique, data output, logic testing, logic testing, delays, integrated circuit testing, application specific integrated circuits, SOC, boundary scan testing
2	Jason Helge Anderson, Chirag Ravishankar	FPGA power reduction by guarded evaluation.	FPGA	2010	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, logic synthesis, technology mapping
2	Sandeep Saini, Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas	An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects.	VLSI Design	2010	DBLP DOI BibTeX RDF	delay reduction, Schmitt Trigger, Buffer Insertion, Power reduction
2	Abhishek A. Sinkar, Nam Sung Kim	Analyzing potential power reduction with adaptive voltage positioning optimized for multicore processors.	ISLPED	2009	DBLP DOI BibTeX RDF	adaptive voltage positioning, multicore processor
2	Qiang Wang, Subodh Gupta, Jason Helge Anderson	Clock power reduction for virtex-5 FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking
2	Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivastava	Code Transformations for TLB Power Reduction.	VLSI Design	2009	DBLP DOI BibTeX RDF
2	Anmol Mathur, Qi Wang	Power Reduction Techniques and Flows at RTL and System Level.	VLSI Design	2009	DBLP DOI BibTeX RDF
2	Weiwei Kang, Steve Hranilovic	Power reduction techniques for multiple-subcarrier modulated diffuse wireless optical channels.	IEEE Transactions on Communications	2008	DBLP DOI BibTeX RDF
2	King Ho Tam, Yu Hu, Lei He, Tom Tong Jing, Xinyi Zhang	Dual-Vdd Buffer Insertion for Power Reduction.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Hassan Hassan, Mohab Anis, Mohamed I. Elmasry	Input Vector Reordering for Leakage Power Reduction in FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault	A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	DfT, Scan, Test data compression, Low power testing
2	Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsusmi, Vasutan Tunbunheng, Hideharu Amano	Power reduction techniques for Dynamically Reconfigurable Processor Arrays.	FPL	2008	DBLP DOI BibTeX RDF
2	Roni Wiener, Gila Kamhi, Moshe Y. Vardi	Intelligate: Scalable Dynamic Invariant Learning for Power Reduction.	PATMOS	2008	DBLP DOI BibTeX RDF
2	Melanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mäding	Scan chain clustering for test power reduction.	DAC	2008	DBLP DOI BibTeX RDF	test, low power, design for test, scan design
2	Min Ni, Seda Ogrenci Memik	Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction.	DAC	2008	DBLP DOI BibTeX RDF	dual-Vth, leakage power optimization, gate sizing, clock skew scheduling
2	Liting Hu, Hai Jin, Xiaofei Liao, Xianjie Xiong, Haikun Liu	Magnet: A novel scheduling policy for power reduction in cluster with virtual machines.	CLUSTER	2008	DBLP DOI BibTeX RDF
2	Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Ali-Asghar Salehpour, Ali Afzali-Kusha, Zainalabedin Navabi	Stall Power Reduction in Pipelined Architecture Processors.	VLSI Design	2008	DBLP DOI BibTeX RDF
2	Jia Li, Qiang Xu, Yu Hu, Xiaowei Li	iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing.	DATE	2008	DBLP DOI BibTeX RDF
2	Lawrence Leinweber, Swarup Bhunia	Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction.	DATE	2008	DBLP DOI BibTeX RDF
2	Michael A. Baker, Viswesh Parameswaran, Karam S. Chatha, Baoxin Li	Power reduction via macroblock prioritization for power aware H.264 video applications.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	low power, video, h.264, voltage scaling, power aware, mpeg4, frequency scaling
2	Elif Alpaslan, Yu Huang 0005, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak	Reducing Scan Shift Power at RTL.	VTS	2008	DBLP DOI BibTeX RDF	Test Power Reduction, Power-Sensitive Scan Cell, RTL DFT, Timing Closure, Scan Based Test
2	Ozgur Sinanoglu	Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Test power reduction, Scan power reduction, Serial transformations, Scan chain modification, Design for testability, Core-based testing
2	Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar	A critical-path-aware partial gating approach for test power reduction.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	partial gating, scan cell gating, Low-power testing, scan testing
2	Fei Li, Yan Lin, Lei He	Field Programmability of Supply Voltages for FPGA Power Reduction.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto	A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari	Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors.	ISPD	2007	DBLP DOI BibTeX RDF	multi-VTH, optimization, timing, low-power design, microprocessor, EDA, leakage power, sizing
2	Lingxiang Xiang, Jiangwei Huang, Weihua Sheng, Tianzhou Chen	The Design and Implementation of the DVS Based Dynamic Compiler for Power Reduction.	APPT	2007	DBLP DOI BibTeX RDF	low power, DVS, dynamic compiler
2	Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M. Rabaey, Kannan Ramchandran	Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya	Power reduction of chip multi-processors using shared resource control cooperating with DVFS.	ICCD	2007	DBLP DOI BibTeX RDF
2	Osamu Muta, Yoshihiko Akaiwa	Peak Power Reduction Method Based on Structure of Parity-Check Matrix for LDPC Coded OFDM Transmission.	VTC Spring	2007	DBLP DOI BibTeX RDF
2	Luca Stabellini, Riccardo Veronesi, Velio Tralli	Increasing System Capacity in GERAN by Means of TRX Power Reduction.	VTC Spring	2007	DBLP DOI BibTeX RDF
2	Michael A. Baker, Aviral Shrivastava, Karam S. Chatha	Smart driver for power reduction in next generation bistable electrophoretic display technology.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	bistable display, display drivers, electrophoretic display, low power display
2	Vassos Soteriou, Noel Eisley, Li-Shiuan Peh	Software-directed power-aware interconnection networks.	TACO	2007	DBLP DOI BibTeX RDF	Software-directed power reduction, simulation, interconnection networks, dynamic voltage scaling, on-chip networks, communication links
2	Satoshi Fukuda, D. Kawazoe, Kenichi Okada, Kazuya Masu	Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation.	ASP-DAC	2007	DBLP DOI BibTeX RDF	intermodulation compensation, reconfigurable CMOS low noise amplifier, variable bias circuit, self compensation, power reduction
2	Hassan Hassan, Mohab Anis, Mohamed I. Elmasry	A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, timing-driven algorithm, MTCMOS FPGA, MTCMOS CAD methodology, subthreshold leakage power reduction, nanometer FPGA, circuit timing information, CMOS process
2	Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera	A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology.	ASP-DAC	2007	DBLP DOI BibTeX RDF	on-chip signaling circuit, impedance-unmatched CML driver, differential transmission-line, CML receiver, CML buffer, load resistance tuning, 10 Gbit/s, CMOS technology, power reduction, 90 nm
2	M. Julia Fernandez-Getino Garcia, Ove Edfors, José Manuel Páez-Borrallo	Peak power reduction for OFDM systems with orthogonal pilot sequences.	IEEE Transactions on Wireless Communications	2006	DBLP DOI BibTeX RDF
2	Yi-Ping You, Chingren Lee, Jenq Kuen Lee	Compilers for leakage power reduction.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Compilers for low power, power-gating mechanisms, leakage-power reduction
2	Yan Lin, Lei He	Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Subash G. Chandar, Mahesh Mehendale, R. Govindarajan	Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF	embedded DSP systems, re-configurable architecture, code compression, energy reduction
2	Kenichi Okada, Takumi Uezono, Kazuya Masu	Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology.	PATMOS	2006	DBLP DOI BibTeX RDF
2	Ji-Yong Jeong, Gil-Su Kim, Jong-Pil Son, Woo-Jin Rim, Soo-Won Kim	Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits.	PATMOS	2006	DBLP DOI BibTeX RDF
2	Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich	Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
2	Yu Hu, Yan Lin, Lei He, Tim Tuan	Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction.	DAC	2006	DBLP DOI BibTeX RDF	FPGA, low power, retiming
2	X.-L. Huang, J.-L. Huang	A routability constrained scan chain ordering technique for test power reduction.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita	A New ATPG Method for Efficient Capture Power Reduction During Scan Testing.	VTS	2006	DBLP DOI BibTeX RDF
2	Taikyeong T. Jeong, Anthony P. Ambler	Design Trade-Offs and Power Reduction Techniques for High Performance Circuits and System.	ICCSA	2006	DBLP DOI BibTeX RDF
2	Osamu Muta, Yoshihiko Akaiwa	A Weighting Factor Estimation Scheme for Phase-Control based Peak Power Reduction of Turbo-coded OFDM signal.	VTC Spring	2006	DBLP DOI BibTeX RDF
2	Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie	Bypass aware instruction scheduling for register file power reduction.	LCTES	2006	DBLP DOI BibTeX RDF	architecture-sensitive compiler, bypass-sensitive, forwarding paths, operation table, processor bypasses, reservation table, power consumption, register file
2	A. Dhammika S. Jayalath, Chintha Tellambura	SLM and PTS peak-power reduction of OFDM signals without side information.	IEEE Transactions on Wireless Communications	2005	DBLP DOI BibTeX RDF
2	Vasanth Venkatachalam, Michael Franz	Power reduction techniques for microprocessor systems.	ACM Comput. Surv.	2005	DBLP DOI BibTeX RDF	power reduction, Energy dissipation
2	Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy	Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning.	ISQED	2005	DBLP DOI BibTeX RDF
2	Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee	A sink-n-hoist framework for leakage power reduction.	EMSOFT	2005	DBLP DOI BibTeX RDF	balanced scheduling, compilers for low power, power-gating mechanisms, data-flow analysis, leakage power reduction
2	Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar	Partial Gating Optimization for Power Reduction During Test Application.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
2	Yan Lin, Lei He	Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction.	DAC	2005	DBLP DOI BibTeX RDF	programmable-Vdd, time slack, FPGA, low power
2	Yan Lin, Fei Li, Lei He	Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González	Software Directed Issue Queue Power Reduction.	HPCA	2005	DBLP DOI BibTeX RDF
2	Vassos Soteriou, Noel Eisley, Li-Shiuan Peh	Software-directed power-aware interconnection networks.	CASES	2005	DBLP DOI BibTeX RDF	dynamic voltage, networks on-a-chip (NoC), software-directed power reduction, simulation, interconnection networks, scaling, communication links
2	Slo-Li Chu	An Energy Reduction Scheduling Mechanism for a High-Performance SoC Architecture.	EUC	2005	DBLP DOI BibTeX RDF	EOPRS, SAGE II, SoC, Power Reduction, Processor-in-Memory
2	Hideki Ochiai	A novel trellis-shaping design with both peak and average power reduction for OFDM systems.	IEEE Transactions on Communications	2004	DBLP DOI BibTeX RDF
2	Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici	Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
2	Yuh-Fang Tsai, D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin	Characterization and modeling of run-time techniques for leakage power reduction.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
2	Sangjin Hong, Shu-Shin Chin, Suhwan Kim, Wei Hwang	Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization.	VLSI Signal Processing	2004	DBLP DOI BibTeX RDF	low-power multiplier, coefficient optimization, power weight factor, power modeling
2	Lucanus J. Simonson, King Ho Tam, Nataraj Akkiraju, Mosur Mohan, Lei He	Leveraging Delay Slack in Flip-Flop and Buffer Insertion for Power Reduction.	ISQED	2004	DBLP DOI BibTeX RDF
2	Fei Li, Yan Lin, Lei He	FPGA power reduction using configurable dual-Vdd.	DAC	2004	DBLP DOI BibTeX RDF	FPGA, low power, configurable, power efficient, dual-Vdd
2	Dan Hillman	Using Mobilize Power Management IP for Dynamic & Static Power Reduction in SoC at 130 nm.	DATE	2004	DBLP DOI BibTeX RDF
2	Jie S. Hu, Narayanan Vijaykrishnan, Soontae Kim, Mahmut T. Kandemir, Mary Jane Irwin	Scheduling Reusable Instructions for Power Reduction.	DATE	2004	DBLP DOI BibTeX RDF
2	Linwei Niu, Gang Quan	Reducing both dynamic and leakage energy consumption for hard real-time systems.	CASES	2004	DBLP DOI BibTeX RDF	embedded system, low power design, DVS, real-time scheduling, leakage power reduction
2	S. Cservany, Jean-Marc Masgonty, Christian Piguet	Stand-by Power Reduction for Storage Circuits.	PATMOS	2003	DBLP DOI BibTeX RDF
2	Masanori Muroyama, Akihiko Hyodo, Takanori Okuma, Hiroto Yasuura	A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits.	DSD	2003	DBLP DOI BibTeX RDF
2	Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy	Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST.	DFT	2003	DBLP DOI BibTeX RDF
2	Amit Singh, Malgorzata Marek-Sadowska	Efficient circuit clustering for area and power reduction in FPGAs.	FPGA	2002	DBLP DOI BibTeX RDF
2	Kun-Wah Yip, Tung-Sang Ng	Additional power reduction offered by fast power control over slow power control in multimedia communications over WLANs.	APCCAS	2002	DBLP DOI BibTeX RDF
2	David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin	Evaluating Run-Time Techniques for Leakage Power Reduction.	VLSI Design	2002	DBLP DOI BibTeX RDF
2	Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici	Scan Architecture for Shift and Capture Cycle Power Reduction. (PDF / PS)	DFT	2002	DBLP DOI BibTeX RDF
2	Stephanie Augsburger, Borivoje Nikolic	Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction.	ICCD	2002	DBLP DOI BibTeX RDF
2	Zhenyu Tang, Lei He, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa	Instruction Prediction for Step Power Reduction.	ISQED	2001	DBLP DOI BibTeX RDF
2	Frank Grassert, Dirk Timmermann	Dynamic single phase logic with self-timed stages for power reduction in pipeline circuit designs.	ISCAS	2001	DBLP DOI BibTeX RDF
2	Xiaodong Zhang, Kaushik Roy	Peak Power Reduction in Low Power BIST.	ISQED	2000	DBLP DOI BibTeX RDF	BIST Synthesis, Weighted Random Pattern Generator, Testing, Low Power
2	Yung-Hsiang Lu, Luca Benini, Giovanni De Micheli	Operating-system directed power reduction.	ISLPED	2000	DBLP DOI BibTeX RDF
2	Yung-Hsiang Lu, Giovanni De Micheli, Luca Benini	Requester-Aware Power Reduction.	ISSS	2000	DBLP DOI BibTeX RDF
2	Tohru Ishihara, Hiroto Yasuura	A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors.	DATE	2000	DBLP DOI BibTeX RDF
2	Pavan Kumar, Mani B. Srivastava	Predictive Strategies for Low-Power RTOS Scheduling. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF	prediction, fixed priority-scheduling, power reduction, real time tasks
2	Qi Wang, Sarma B. K. Vrudhula, Gary K. H. Yeap, Shantanu Ganguly	Power reduction and power-delay trade-offs using logic transformations.	ACM Trans. Design Autom. Electr. Syst.	1999	DBLP DOI BibTeX RDF	CMOS logic, low power, logic synthesis, power estimation, logic optimization
2	Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone	Power reduction through iterative gate sizing and voltage scaling.	ISCAS	1999	DBLP DOI BibTeX RDF
2	Xiaodong Zhang, Kaushik Roy	Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power Reduction. (PDF / PS)	DFT	1999	DBLP DOI BibTeX RDF	BIST Synthesis, Weighted Random Pattern Generator, Low Power BIST, Testing, Low Power, Cellular Automata, Peak Power
2	Ki-Seok Chung, C. L. Liu	Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction.	ISLPED	1998	DBLP DOI BibTeX RDF
2	Johnson Kin, Munish Gupta, William H. Mangione-Smith	The Filter Cache: An Energy Efficient Memory Structure.	MICRO	1997	DBLP BibTeX RDF	direct mapped 256-byte filter cache, energy efficient memory structure, on-chip caches, static RAM, microprocessors, microprocessor chips, power reduction, embedded applications, L2 cache, filter cache, L1 cache
2	Prakash Arunachalam, Jacob A. Abraham, Manuel A. d'Abreu	A Hierarchal Approach for Power Reduction in VLSI Chips. (PDF / PS)	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
2	Inki Hong, Miodrag Potkonjak	Power optimization in disk-based real-time application specific systems.	ICCAD	1996	DBLP DOI BibTeX RDF	design process abstractions, disk data assignment, electronic components, magnetic disks, mechanical-electronic subsystems, power consumption model, real-time application specific systems, task scheduling, power optimization, power reduction, power minimization, magnetic disc storage, disk drives
2	Hans Lindkvist, Per Andersson	Dynamic CMOS circuit techniques for delay and power reduction in parallel adders .	ARVLSI	1995	DBLP DOI BibTeX RDF	dynamic CMOS circuit techniques, delay reduction, parallel adders, high-speed adders, Manchester-carry chains, clock/data precharged dynamic logic blocks, carry calculation trees, parallel processing, VLSI, delays, logic design, digital arithmetic, power consumption, adders, CMOS logic circuits, power reduction, carry logic
2	C. Farnsworth, David A. Edwards, Jianwei Liu, S. S. Sikand	A hybrid asynchronous system design environment.	ASYNC	1995	DBLP DOI BibTeX RDF	hybrid asynchronous system design environment, hybrid design scheme, asynchronous circuit synthesis, Tangram silicon complier, synchronous design techniques, concurrency, high level synthesis, asynchronous circuits, power reduction, performance gains, micropipelines
2	Hiroaki Ueda, Kozo Kinoshita	Low power design and its testability.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	power reduction tool, power dissipation factor, testability parameters, fault diagnosis, logic testing, delays, probability, design for testability, low power design, logic CAD, testability, fault location, stuck-at faults, CMOS logic circuits, delay faults, CMOS circuit, PORT, automatic test software, redundant faults, transition probability
1	Yusuf Adibelli, Mustafa Parlak, Ilker Hamzaoglu	Computation and power reduction techniques for H.264 intra prediction.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Christos Masouros, Mathini Sellathurai, Tharmalingam Ratnarajah	Interference Optimization for Transmit Power Reduction in Tomlinson-Harashima Precoded MIMO Downlinks.	IEEE Transactions on Signal Processing	2012	DBLP DOI BibTeX RDF