| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Weixun Wang, Prabhat Mishra |
System-Wide Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Multitasking Systems.  |
IEEE Trans. VLSI Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kamran Rahmani, Prabhat Mishra, Swarup Bhunia |
Memory-based computing for performance and energy improvement in multicore architectures. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kamran Rahmani, Hadi Hajimiri, Kartik Shrivastava, Prabhat Mishra |
Synergistic integration of code encryption and compression in embedded systems. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhe Wang, Sanjay Ranka, Prabhat Mishra |
Temperature-aware Task Partitioning for Real-Time Scheduling in Embedded Systems. |
VLSI Design |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hadi Hajimiri, Prabhat Mishra |
Intra-Task Dynamic Cache Reconfiguration. |
VLSI Design |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoke Qin, Prabhat Mishra |
Automated generation of directed tests for transition coverage in cache coherence protocols. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Weixun Wang, Prabhat Mishra |
Dynamic Reconfiguration of Two-Level Cache Hierarchy in Real-Time Embedded Systems. |
J. Low Power Electronics |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mingsong Chen, Prabhat Mishra |
Property Learning Techniques for Efficient Generation of Directed Tests. |
IEEE Trans. Computers |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoke Qin, Chetan Muthry, Prabhat Mishra |
Decoding-Aware Compression of FPGA Bitstreams. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandeep K. Shukla, Prabhat Mishra, Zeljko Zilic |
A Brief History of Multiprocessors and EDA. |
IEEE Design & Test of Computers |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Zeljko Zilic, Prabhat Mishra, Sandeep K. Shukla |
Challenges of Rapidly Emerging Consumer Space Multiprocessors. |
IEEE Design & Test of Computers |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Prabhat Mishra, Zeljko Zilic, Sandeep K. Shukla |
Guest Editors' Introduction: Multicore SoC Validation with Transaction-Level Models. |
IEEE Design & Test of Computers |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoke Qin, Prabhat Mishra |
Efficient directed test generation for validation of multicore architectures. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanad Basu, Prabhat Mishra, Priyadarsan Patra |
Efficient combination of trace and scan signals for post silicon validation and debug. |
ITC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Weixun Wang, Prabhat Mishra, Sanjay Ranka |
Dynamic cache reconfiguration and partitioning for energy optimization in real-time multi-core systems. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanad Basu, Prabhat Mishra |
Efficient trace data compression using statically selected dictionary. |
VTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kartik Shrivastava, Prabhat Mishra |
Dual Code Compression for Embedded Systems. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Weixun Wang, Sanjay Ranka, Prabhat Mishra |
A General Algorithm for Energy-Aware Dynamic Reconfiguration in Multitasking Systems. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanad Basu, Prabhat Mishra |
Efficient Trace Signal Selection for Post Silicon Validation and Debug. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mingsong Chen, Prabhat Mishra |
Decision ordering based property decomposition for functional test generation. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mingsong Chen, Prabhat Mishra, Dhrubajyoti Kalita |
Efficient test case generation for validation of UML activity diagrams. |
Design Autom. for Emb. Sys. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mingsong Chen, Prabhat Mishra |
Functional Test Generation Using Efficient Property Clustering and Learning Techniques. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanad Basu, Prabhat Mishra |
Test Data Compression Using Efficient Bitmask and Dictionary Selection Methods. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Prabhat Mishra |
Guest Editorial. |
J. Electronic Testing |
2010 |
DBLP BibTeX RDF |
|
| 1 | Weixun Wang, Xiaoke Qin, Prabhat Mishra |
Temperature- and energy-constrained scheduling in multitasking systems: a model checking approach. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
dvs, temperature-aware, model checking, low power design |
| 1 | Weixun Wang, Prabhat Mishra |
PreDVS: preemptive dynamic voltage scaling for real-time systems using approximation scheme. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
real-time systems, approximation algorithm, dynamic voltage scaling, energy-aware scheduling |
| 1 | Sanjay Ranka, Arunava Banerjee, Kanad Kishore Biswas, Sumeet Dua, Prabhat Mishra, Rajat Moona, Sheung-Hung Poon, Cho-Li Wang (eds.) |
Contemporary Computing - Third International Conference, IC3 2010, Noida, India, August 9-11, 2010, Proceedings, Part II |
IC3 |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sanjay Ranka, Arunava Banerjee, Kanad Kishore Biswas, Sumeet Dua, Prabhat Mishra, Rajat Moona, Sheung-Hung Poon, Cho-Li Wang (eds.) |
Contemporary Computing - Third International Conference, IC3 2010, Noida, India, August 9-11, 2010. Proceedings, Part I |
IC3 |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Weixun Wang, Prabhat Mishra |
Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Real-Time Systems. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoke Qin, Mingsong Chen, Prabhat Mishra |
Synchronized Generation of Directed Tests Using Satisfiability Solving. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
Directed test generation, SAT solving |
| 1 | Mingsong Chen, Xiaoke Qin, Prabhat Mishra |
Efficient decision ordering techniques for SAT-based test generation. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Prabhat Mishra |
Guest Editor Introduction: Special Issue on Nano/Bio-Inspired Applications and Architectures. |
International Journal of Parallel Programming |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt |
Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation. |
ACM Trans. Embedded Comput. Syst. |
2009 |
DBLP DOI BibTeX RDF |
interpretive simulation, partial evaluation, instruction set architecture, Compiled simulation |
| 1 | Heon-Mo Koo, Prabhat Mishra |
Functional test generation using design and property decomposition techniques. |
ACM Trans. Embedded Comput. Syst. |
2009 |
DBLP DOI BibTeX RDF |
design decomposition, property decomposition, Model checking, test generation, pipelined processor, functional validation |
| 1 | Xiaoke Qin, Prabhat Mishra |
A Universal Placement Technique of Compressed Instructions for Efficient Parallel Decompression. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Weixun Wang, Prabhat Mishra |
Dynamic Reconfiguration of Two-Level Caches in Soft Real-Time Embedded Systems. |
ISVLSI |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chetan Murthy, Prabhat Mishra |
Lossless Compression Using Efficient Encoding of Bitmasks. |
ISVLSI |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Priyank Kalla, Prabhat Mishra |
Chairs' welcome message. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chetan Murthy, Prabhat Mishra |
Bitmask-based control word compression for NISC architectures. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
no instruction set computer, compression |
| 1 | Thanh Nga Dang, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra |
Generating test programs to cover pipeline interactions. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
pipelines, automated test generation, state space exploration |
| 1 | Weixun Wang, Prabhat Mishra, Ann Gordon-Ross |
SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoke Qin, Prabhat Mishra |
Efficient Placement of Compressed Code for Parallel Decompression. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Prabhat Mishra, Mingsong Chen |
Efficient Techniques for Directed Test Generation Using Incremental Satisfiability. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Prabhat Mishra, Nikil Dutt |
Specification-driven directed test generation for validation of pipelined processors. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
Model checking, test generation, functional validation |
| 1 | Seok-Won Seong, Prabhat Mishra |
Bitmask-Based Code Compression for Embedded Systems. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Mingsong Chen, Prabhat Mishra, Dhrubajyoti Kalita |
Coverage-driven automatic test generation for uml activity diagrams. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
uml activity diagrams, test generation |
| 1 | Kanad Basu, Prabhat Mishra |
A novel test-data compression technique using application-aware bitmask and dictionary selection methods. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
compression, test data, decompression |
| 1 | Heon-Mo Koo, Prabhat Mishra |
Specification-based compaction of directed tests for functional validation of pipelined processors. |
CODES+ISSS |
2008 |
DBLP DOI BibTeX RDF |
processor validation, test compaction |
| 1 | Xianfeng Li, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra, Xu Cheng |
A Retargetable Software Timing Analyzer Using Architecture Description Language. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
retargetable software timing analyzer, static WCET analysis, program path analysis, microarchitecture modeling, graph-based execution models, pipeline model, real-time systems, architecture description language, worst case execution time, embedded processors, branch prediction, schedulability analysis |
| 1 | Seok-Won Seong, Prabhat Mishra |
An efficient code compression technique using application-aware bitmask and dictionary selection methods. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehrdad Reshadi, Nikil Dutt, Prabhat Mishra |
A retargetable framework for instruction-set architecture simulation. |
ACM Trans. Embedded Comput. Syst. |
2006 |
DBLP DOI BibTeX RDF |
Retargetable instruction-set simulation, generic instruction model, instruction binary encoding, architecture description language, decode algorithm |
| 1 | Prabhat Mishra, Aviral Shrivastava, Nikil Dutt |
Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs. |
ACM Trans. Design Autom. Electr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
programmable architecture, design space exploration, Architecture description language, embedded processor, retargetable compilation |
| 1 | Heon-Mo Koo, Prabhat Mishra |
Test generation using SAT-based bounded model checking for validation of pipelined processors. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
test generation, functional validation |
| 1 | Heon-Mo Koo, Prabhat Mishra |
Functional test generation using property decompositions for validation of pipelined processors. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy S. Abadir |
Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study. |
MTV |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Seok-Won Seong, Prabhat Mishra |
A bitmask-based code compression technique for embedded systems. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Prabhat Mishra, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir |
A methodology for validation of microprocessors using symbolic simulation. |
IJES |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Prabhat Mishra, Nikil D. Dutt |
Functional verification of programmable embedded architectures - a top-down approach. |
|
2005 |
RDF |
|
| 1 | Prabhat Mishra, Nikil D. Dutt |
Functional Coverage Driven Test Generation for Validation of Pipelined Processors. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Prabhat Mishra, Heon-Mo Koo, Zhuo Huang |
Language-driven Validation of Pipelined Processors using Satisfiability Solvers. |
MTV |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehrdad Reshadi, Prabhat Mishra |
Memory access optimizations in instruction-set simulators. |
CODES+ISSS |
2005 |
DBLP DOI BibTeX RDF |
memory address-space mapping, instruction-set simulator |
| 1 | Prabhat Mishra, Mahesh Mamidipaka, Nikil Dutt |
Processor-memory coexploration using an architecture description language. |
ACM Trans. Embedded Comput. Syst. |
2004 |
DBLP DOI BibTeX RDF |
Processor-memory codesign, memory exploration, design space exploration, architecture description language |
| 1 | Prabhat Mishra, Nikil Dutt |
Modeling and validation of pipeline specifications. |
ACM Trans. Embedded Comput. Syst. |
2004 |
DBLP DOI BibTeX RDF |
Modeling of processor pipeline, pipeline validation, pipelined processor specification, architecture description language |
| 1 | Prabhat Mishra, Nikil Dutt, Narayanan Krishnamurthy, Magdy S. Abadir |
A Top-Down Methodology for Microprocessor Validation. |
IEEE Design & Test of Computers |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Prabhat Mishra, Nikil D. Dutt |
Functional Validation of Programmable Architectures. |
DSD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Prabhat Mishra, Arun Kejariwal, Nikil Dutt |
Synthesis-driven Exploration of Pipelined Embedded Processors. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Prabhat Mishra, Nikil Dutt |
Graph-Based Functional Test Program Generation for Pipelined Processors. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Prabhat Mishra, Nikil D. Dutt, Yaron Kashai |
Functional Verification of Pipelined Processors: A Case Study. |
MTV |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Prabhat Mishra, Nikil Dutt, Hiroyuki Tomiyama |
Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications. |
Design Autom. for Emb. Sys. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Prabhat Mishra, Arun Kejariwal, Nikil Dutt |
Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models. |
IEEE International Workshop on Rapid System Prototyping |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt |
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
instruction abstraction, interpretive simulation, instruction set architectures, compiled simulation |
| 1 | Prabhat Mishra, Nikil D. Dutt |
A Methodology for Validation of Microprocessors using Equivalence Checking. |
MTV |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehrdad Reshadi, Nikhil Bansal, Prabhat Mishra, Nikil D. Dutt |
An efficient retargetable framework for instruction-set simulation. |
CODES+ISSS |
2003 |
DBLP DOI BibTeX RDF |
generic instruction model, instruction binary encoding, retargetable instruction-set simulation, architecture description language, decode algorithm |
| 1 | Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau |
Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
Pipeline Verification, Architecture Description Language |
| 1 | Prabhat Mishra, Nikil D. Dutt |
Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions. |
DIPES |
2002 |
DBLP BibTeX RDF |
|
| 1 | Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama |
Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau |
Functional abstraction driven design space exploration of heterogeneous programmable architectures. |
ISSS |
2001 |
DBLP BibTeX RDF |
|
| 1 | Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexandru Nicolau |
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
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