Search results for "Pradip Bose"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Meeta Sharma Gupta, Michael B. Healy, Hans M. Jacobson, Indira Nair, Jude A. Rivers, Jeonghee Shin, Augusto Vega, Alan J. Weger	Power management of multi-core chips: Challenges and pitfalls.	DATE	2012	DBLP BibTeX RDF
1	Augusto Vega, Pradip Bose, Alper Buyuktosunoglu, Jeff H. Derby, Michele Franceschini, Charles Johnson, Robert K. Montoye	Architectural perspectives of future wireless base stations based on the IBM PowerEN™ processor.	HPCA	2012	DBLP DOI BibTeX RDF
1	Victor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Eren Kursun, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero	Energy-Aware Accounting and Billing in Large-Scale Computing Facilities.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Michael S. Floyd, Malcolm Allen-Ware, Karthick Rajamani, Bishop Brock, Charles Lefurgy, Alan J. Drake, Lorena Pesantez, Tilman Gloekler, José A. Tierno, Pradip Bose, Alper Buyuktosunoglu	Introducing the Adaptive Energy Management Features of the Power7 Chip.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Jude A. Rivers, Meeta Sharma Gupta, Jeonghee Shin, Prabhakar Kudva, Pradip Bose	Error Tolerance in Server Class Processors.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Michael S. Floyd, Malcolm Allen-Ware, Karthick Rajamani, Tilman Gloekler, Bishop Brock, Pradip Bose, Alper Buyuktosunoglu, Juan C. Rubio, Birgit Schubert, Bruno Spruth, José A. Tierno, Lorena Pesantez	Adaptive energy-management features of the IBM POWER7 chip.	IBM Journal of Research and Development	2011	DBLP DOI BibTeX RDF
1	Pradip Bose	Power Wall.	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
1	Pradip Bose	Keynote II: Integrated modeling challenges in extreme-scale computing.	ISPASS	2011	DBLP DOI BibTeX RDF
1	Amlan Ganguly, Partha Kundu, Pradip Bose	Curbing energy cravings in networks: A cross-sectional view across the micro-macro boundary.	NOCS	2011	DBLP BibTeX RDF
1	Hans M. Jacobson, Alper Buyuktosunoglu, Pradip Bose, Emrah Acar, Richard J. Eickemeyer	Abstraction and microarchitecture scaling in early-stage power modeling.	HPCA	2011	DBLP DOI BibTeX RDF
1	Niti Madan, Alper Buyuktosunoglu, Pradip Bose, Murali Annavaram	A case for guarded power gating for multi-core processors.	HPCA	2011	DBLP DOI BibTeX RDF
1	Niti Madan, Alper Buyuktosunoglu, Pradip Bose, Murali Annavaram	Guarded Power Gating in a Multi-core Setting.	ISCA Workshops	2010	DBLP DOI BibTeX RDF
1	Victor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose	Power and thermal characterization of POWER6 system.	PACT	2010	DBLP DOI BibTeX RDF
1	Victor Jiménez, Roberto Gioiosa, Eren Kursun, Francisco J. Cazorla, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero	Trends and techniques for energy efficient architectures.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger, Victor V. Zyuban	Power-efficient, reliable microprocessor architectures: modeling and design methods.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	power-efficient design, pre-silicon modeling, reliable operation
1	Alejandro Rico, Jeff H. Derby, Robert K. Montoye, Timothy H. Heil, Chen-Yong Cher, Pradip Bose	Performance and power evaluation of an in-line accelerator.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	vmx, accelerator, powerpc, simd
1	Matthew T. Jacob, Chita R. Das, Pradip Bose (eds.)	16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 9-14 January 2010, Bangalore, India	HPCA	2010	DBLP BibTeX RDF
1	Yu Cao, Jim Tschanz, Pradip Bose	Guest Editors' Introduction: Reliability Challenges in Nano-CMOS Design.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Anita Lungu, Pradip Bose, Daniel J. Sorin, Steven German, Geert Janssen	Multicore power management: Ensuring robustness via early-stage formal verification.	MEMOCODE	2009	DBLP DOI BibTeX RDF
1	Anita Lungu, Pradip Bose, Alper Buyuktosunoglu, Daniel J. Sorin	Dynamic power gating with quality guarantees.	ISLPED	2009	DBLP DOI BibTeX RDF	execution units, low power, power management, microarchitecture, power gating
1	Meeta Sharma Gupta, Jude A. Rivers, Pradip Bose, Gu-Yeon Wei, David Brooks	Tribeca: design for PVT variations with local recovery and fine-grained adaptation.	MICRO	2009	DBLP DOI BibTeX RDF
1	Jude A. Rivers, Pradip Bose, Prabhakar Kudva, John-David Wellman, Pia N. Sanda, Ethan H. Cannon, Luiz C. Alves	Phaser: Phased methodology for modeling the system-level effects of soft errors.	IBM Journal of Research and Development	2008	DBLP DOI BibTeX RDF
1	Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers	Online Estimation of Architectural Vulnerability Factor for Soft Errors.	ISCA	2008	DBLP DOI BibTeX RDF
1	Jeonghee Shin, Victor V. Zyuban, Pradip Bose, Timothy Mark Pinkston	A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime.	ISCA	2008	DBLP DOI BibTeX RDF
1	Pradeep Ramachandran, Sarita V. Adve, Pradip Bose, Jude A. Rivers	Metrics for Architecture-Level Lifetime Reliability Analysis.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Reinaldo A. Bergamaschi, Guoling Han, Alper Buyuktosunoglu, Hiren D. Patel, Indira Nair, Gero Dittmann, Geert Janssen, Nagu R. Dhanwada, Zhigang Hu, Pradip Bose, John A. Darringer	Exploring power management in multi-core systems.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Aneesh Aggarwal, Pradip Bose, Mohamed Zahran	Introduction to the special issue on the 2006 reconfigurable and adaptive architecture workshop.	SIGARCH Computer Architecture News	2007	DBLP DOI BibTeX RDF
1	Kevin Skadron, Pradip Bose, Kanad Ghose, Resit Sendag, Joshua J. Yi, Derek Chiou	Low-Power Design and Temperature Management.	IEEE Micro	2007	DBLP DOI BibTeX RDF	low-power design, power management, hardware, energy-aware systems, temperature-aware design
1	Jeonghwan Choi, Chen-Yong Cher, Hubertus Franke, Hendrik F. Hamann, Alan J. Weger, Pradip Bose	Thermal-aware task scheduling at the system software level.	ISLPED	2007	DBLP DOI BibTeX RDF	low-power design, repeater insertion, temperature-aware design
1	Joseph J. Sharkey, Alper Buyuktosunoglu, Pradip Bose	Evaluating design tradeoffs in on-chip power management for CMPs.	ISLPED	2007	DBLP DOI BibTeX RDF	fetch throttling, dynamic voltage scaling, power-aware, chip multi-processor
1	Jeonghee Shin, Victor V. Zyuban, Zhigang Hu, Jude A. Rivers, Pradip Bose	A Framework for Architecture-Level Lifetime Reliability Modeling.	DSN	2007	DBLP DOI BibTeX RDF
1	Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers	Architecture-Level Soft Error Analysis: Examining the Limits of Common Assumptions.	DSN	2007	DBLP DOI BibTeX RDF
1	Hendrik F. Hamann, Alan J. Weger, James A. Lacey, Zhigang Hu, Pradip Bose, Erwin Cohen, Jamil A. Wakil	Temperature-limited microprocessors: Measurements and design implications.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han	Performance modeling for early analysis of multi-core systems.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	early analysis, multi-core systems modeling, physical analysis, performance, power analysis, transaction-level modeling
1	Pradip Bose	Pre-Silicon Modeling and Analysis: Impact On Real Design.	IEEE Micro	2006	DBLP DOI BibTeX RDF	Pre-silicon modeling, performance modeling, CMOS
1	Pradip Bose	Robust On-Chip Communication.	IEEE Micro	2006	DBLP DOI BibTeX RDF	high-performance computing, on-chip interconnects
1	Pradip Bose	Workload characterization: A key aspect of microarchitecture design.	IEEE Micro	2006	DBLP DOI BibTeX RDF	target workloads, microarchitecture design, workload characterization
1	Pradip Bose	Looking briefly back, and then forward...	IEEE Micro	2006	DBLP DOI BibTeX RDF	computer architecture, hardware
1	Pradip Bose	Measuring the impact of microarchitectural ideas.	IEEE Micro	2006	DBLP DOI BibTeX RDF	Top Picks, IEEE Micro, microarchitecture
1	Pradip Bose	Designing reliable systems with unreliable components.	IEEE Micro	2006	DBLP DOI BibTeX RDF	reliable components, reliable systems
1	Canturk Isci, Alper Buyuktosunoglu, Chen-Yong Cher, Pradip Bose, Margaret Martonosi	An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget.	MICRO	2006	DBLP DOI BibTeX RDF
1	Pradip Bose	Presilicon modeling: challenges in the late CMOS era.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Integrated microarchitectures, special purpose accelerators, scalable on-chip interconnection network, presilicon modeling, CMOS
1	Pradip Bose	Variation-tolerant design.	IEEE Micro	2005	DBLP DOI BibTeX RDF
1	Pradip Bose	Designing microprocessors with robust functionality and performance.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Reliability-aware microarchitecture, power-efficient design, microprocessor design
1	Kunio Uchiyama, Pradip Bose	Guest Editors' Introduction: Energy-Efficient Design.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Cool Chips VII, ACEED, Cell processor, Energy-efficient design
1	Pradip Bose	High performance at affordable power.	IEEE Micro	2005	DBLP DOI BibTeX RDF	affordable power, Energy efficiency, high performance
1	Pradip Bose	The "power" of communication.	IEEE Micro	2005	DBLP DOI BibTeX RDF
1	Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers	Lifetime Reliability: Toward an Architectural Solution.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Lifetime reliability, RAMP, power management, scaling, DRM, MTTF
1	Pradip Bose	Integrated microarchitectures.	IEEE Micro	2005	DBLP DOI BibTeX RDF
1	Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers	Exploiting Structural Duplication for Lifetime Reliability Enhancement.	ISCA	2005	DBLP DOI BibTeX RDF
1	Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers	SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft Errors.	DSN	2005	DBLP DOI BibTeX RDF
1	Pradip Bose	Power-Aware, Reliable Microprocessor Design. (PDF / PS)	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler	Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors.	HPCA	2005	DBLP DOI BibTeX RDF
1	Pradip Bose	EIC's Message: General-purpose versus application-specific processors.	IEEE Micro	2004	DBLP DOI BibTeX RDF
1	Pradip Bose	Editor in Chief's Message: New Challenges and Burning Issues.	IEEE Micro	2004	DBLP DOI BibTeX RDF
1	Pradip Bose	Editor in Chief's Message: Saving power-Lessons from embedded systems.	IEEE Micro	2004	DBLP DOI BibTeX RDF
1	Pradip Bose	EIC's Message: Chip-level microarchitecture trends.	IEEE Micro	2004	DBLP DOI BibTeX RDF
1	Pradip Bose	Computer architecture research: Shifting priorities and newer challenges.	IEEE Micro	2004	DBLP DOI BibTeX RDF
1	Pradip Bose	Communication versus Computation.	IEEE Micro	2004	DBLP DOI BibTeX RDF
1	Victor V. Zyuban, David Brooks, Viji Srinivasan, Michael Gschwind, Pradip Bose, Philip N. Strenski, Philip G. Emma	Integrated Analysis of Power and Performance for Pipelined Microprocessors.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
1	David Brooks, Pradip Bose, Margaret Martonosi	Power-performance simulation: design and validation strategies.	SIGMETRICS Performance Evaluation Review	2004	DBLP DOI BibTeX RDF
1	Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers	The Case for Lifetime Reliability-Aware Microprocessors.	ISCA	2004	DBLP DOI BibTeX RDF
1	Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose	Microarchitectural techniques for power gating of execution units.	ISLPED	2004	DBLP DOI BibTeX RDF	execution units, low power, microarchitecture, power-gating
1	Yingmin Li, David Brooks, Zhigang Hu, Kevin Skadron, Pradip Bose	Understanding the energy efficiency of simultaneous multithreading.	ISLPED	2004	DBLP DOI BibTeX RDF	multithreading
1	Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers	The Impact of Technology Scaling on Lifetime Reliability.	DSN	2004	DBLP DOI BibTeX RDF
1	Pradip Bose	Looking Forward to Bright New Beginnings.	IEEE Micro	2003	DBLP DOI BibTeX RDF
1	Charles R. Moore, Kevin W. Rudd, Ruby B. Lee, Pradip Bose	Guest Editors' Introduction: Micro's Top Picks from Microarchitecture Conferences.	IEEE Micro	2003	DBLP DOI BibTeX RDF
1	Pradip Bose	Editor-in-Chief?s Message: Adapting Old Paradigms to Meet New Challenges. (PDF / PS)	IEEE Micro	2003	DBLP DOI BibTeX RDF
1	Pradip Bose	Issues and Trends in High-Performance Processor Cores. (PDF / PS)	IEEE Micro	2003	DBLP DOI BibTeX RDF
1	Pradip Bose	Design and Integration: Chip- and System-Level Challenges. (PDF / PS)	IEEE Micro	2003	DBLP DOI BibTeX RDF
1	Pradip Bose, David H. Albonesi, Diana Marculescu	Guest Editors' Introduction: Power and Complexity Aware Design.	IEEE Micro	2003	DBLP DOI BibTeX RDF
1	David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster	Dynamically Tuning Processor Resources with Adaptive Processing.	IEEE Computer	2003	DBLP DOI BibTeX RDF
1	David Brooks, Pradip Bose, Viji Srinivasan, Michael Gschwind, Philip G. Emma, Michael G. Rosenfield	New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors.	IBM Journal of Research and Development	2003	DBLP DOI BibTeX RDF
1	Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose	Energy Efficient Co-Adaptive Instruction Fetch and Issue. (PDF / PS)	ISCA	2003	DBLP DOI BibTeX RDF
1	Alper Buyuktosunoglu, David H. Albonesi, Pradip Bose, Peter W. Cook, Stanley Schuster	Tradeoffs in power-efficient issue queue design.	ISLPED	2002	DBLP DOI BibTeX RDF	non-compacting, adaptation, low-power, microarchitecture, compacting, banking, issue queue
1	Tejas Karkhanis, James E. Smith, Pradip Bose	Saving energy with just in time instruction delivery.	ISLPED	2002	DBLP DOI BibTeX RDF	adaptive processor, low-power, instruction delivery
1	Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Peter W. Cook, Stanley Schuster	Synchronous Interlocked Pipelines.	ASYNC	2002	DBLP BibTeX RDF	progressive stalls, synchronous, Pipeline, asynchronous, clock gating, elastic, interlocked
1	Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma	Optimizing pipelines for power and performance.	MICRO	2002	DBLP DOI BibTeX RDF
1	Pradip Bose, David Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas	Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.	PACS	2002	DBLP DOI BibTeX RDF
1	Alper Buyuktosunoglu, David H. Albonesi, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook	A circuit level implementation of an adaptive issue queue for power-aware microprocessors.	ACM Great Lakes Symposium on VLSI	2001	DBLP DOI BibTeX RDF
1	Pradip Bose	Ensuring Dependable Processor Performance: An Experience Report on Pre-Silicon Performance Validation.	DSN	2001	DBLP DOI BibTeX RDF
1	David Brooks, Pradip Bose, Stanley Schuster, Hans M. Jacobson, Prabhakar Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor V. Zyuban, Manish Gupta, Peter W. Cook	Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors.	IEEE Micro	2000	DBLP DOI BibTeX RDF
1	Pradip Bose	Testing for Function and Performance: Towards an Integrated Processor Validation Methodology.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	performance test cases, bounds modeling, performance validation, integrated methodology, test generation, microprocessor testing
1	David Brooks, Margaret Martonosi, John-David Wellman, Pradip Bose	Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor.	PACS	2000	DBLP DOI BibTeX RDF
1	Alper Buyuktosunoglu, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook, David H. Albonesi	An Adaptive Issue Queue for Reduced Power at High Performance.	PACS	2000	DBLP DOI BibTeX RDF
1	Pradip Bose, Jacob A. Abraham	Performance and Functional Verification of Microprocessors.	VLSI Design	2000	DBLP DOI BibTeX RDF
1	Pradip Bose, Sunil Kim, Francis P. O'Connell, William A. Ciarfella	Bounds modelling and compiler optimizations for superscalar performance tuning.	Journal of Systems Architecture	1999	DBLP DOI BibTeX RDF
1	Pradip Bose	Performance Evaluation and Validation of Microprocessors.	SIGMETRICS	1999	DBLP DOI BibTeX RDF	performance evaluation, validation, processor design
1	Pradip Bose, Thomas M. Conte	Performance Analysis and Its Impact on Design.	IEEE Computer	1998	DBLP DOI BibTeX RDF
1	Pradip Bose	Performance Test Case Generation for Microprocessors. (PDF / PS)	VTS	1998	DBLP DOI BibTeX RDF
1	Pradip Bose	Preface.	IBM Journal of Research and Development	1997	DBLP DOI BibTeX RDF
1	Anthony-Trung Nguyen, Pradip Bose, Kattamuri Ekanadham, Ashwini K. Nanda, Maged M. Michael	Accuracy and Speedup of Parallel Trace-Driven Architectural Simulation. (PDF / PS)	IPPS	1997	DBLP DOI BibTeX RDF
1	Vijay S. Iyengar, Louise Trevillyan, Pradip Bose	Representative Traces for Processor Models with Infinite Cache.	HPCA	1996	DBLP DOI BibTeX RDF	dynamic traces, performance evaluation, timer, processor design
1	Pradip Bose, S. Surya	Architectural timing verification of CMOS RISC processors.	IBM Journal of Research and Development	1995	DBLP BibTeX RDF
1	Pradip Bose	Architectural Timing Verification and Test for Super Scalar Processors.	FTCS	1994	DBLP DOI BibTeX RDF
1	S. Surya, Pradip Bose, Jacob A. Abraham	Architectural Performance Verification: PowerPCTM Processors.	ICCD	1994	DBLP BibTeX RDF
1	Pradip Bose, John-David Wellman	MIPS-Driven Early Design and Analysis of VLSI CPU Chips.	VLSI Design	1993	DBLP BibTeX RDF
1	Pradip Bose, David LaPotin, Gopalakrishnan Vijayan, Sungho Kim	Workload-Driven Floorplanning for MIPS Optimization.	ICCD	1992	DBLP BibTeX RDF
1	Pradip Bose	Early Performance Estimation of Super Scalar Machine Models.	ICCD	1991	DBLP BibTeX RDF
1	Pradip Bose	A Novel Technique for Efficient Parallel Implementation of a Classical Logic/Fault Simulation Problem.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF

Publications of "Pradip Bose" ( http://dblp.L3S.de/Authors/Pradip_Bose )