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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 11 occurrences of 11 keywords
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Results
Found 37 publication records. Showing 37 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Kaushik Bhattacharyya, Pradip Mandal |
Improvement of Performance of Dynamically Reconfigurable Switched Capacitor Based Non-Overlap Rotational Time Interleaved Embedded DC-DC Converter.  |
J. Low Power Electronics  |
2012 |
DBLP BibTeX RDF |
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| 1 | Biswajit Maity, Soumya Gangula, Pradip Mandal |
Design and Implementation of an Area and Power Efficient Switched-Capacitor Based Embedded DC-DC Converter. |
J. Low Power Electronics |
2012 |
DBLP BibTeX RDF |
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| 1 | Kaushik Bhattacharyya, P. V. Ratna Kumar, Pradip Mandal |
Improvement of Power Efficiency and output voltage Ripple of Embedded DC-DC converters with Three Step Down ratios. |
Journal of Circuits, Systems, and Computers |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Supriyo Maji, Pradip Mandal |
Effcient approaches to overcome non-convexity issues in analog design automation. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Samiran Dam, Pradip Mandal |
Iterative Performance Model Upgradation in Geometric Programming Based Analog Circuit Sizing for Improved Design Accuracy. |
VLSI Design |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Supriyo Maji, Pradip Mandal |
A Fast Equation Free Iterative Approach to Analog Circuit Sizing. |
VLSI Design |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Kaushik Bhattacharyya, Pradip Mandal |
A dynamically reconfigurable NRTI switched-capacitor-based hybrid DC-DC converter suitable for embedded applications. |
Microelectronics Journal |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | P. Vijaya Sankara Rao, Pradip Mandal |
Current-mode full-duplex (CMFD) signaling for high-speed chip-to-chip interconnect. |
Microelectronics Journal |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Supriyo Maji, Samiran Dam, Pradip Mandal |
Automatic generation of saturation constraints and performance expressions for geometric programming based analog circuit sizing. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Sabyasachi Deyati, Pradip Mandal |
An automated design methodology for yield aware analog circuit synthesis in submicron technology. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Supriyo Maji, Pradip Mandal |
A geometric programming aided knowledge based approach for analog circuit synthesis and sizing. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Mrigank Sharad, P. Vijaya Sankara Rao, Pradip Mandal |
A New Double Data Rate(DDR) Dual-Mode Duobinary Transmitter Architecture. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Supriyo Maji, Pradip Mandal |
A CAD methodology for automatic topology selection & sizing. |
SoCC |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Samiran DasGupta, Pradip Mandal |
An Improvised MOS Transistor Model Suitable for Geometric Program Based Analog Circuit Sizing in Sub-micron Technology. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
opamp, submicron sizing, design automation, geometric program |
| 1 | Tamal Das, Pradip Mandal |
On-Chip Inductor-Less DC-DC Boost Converter with Non-overlapped Rotational-Interleaving Scheme. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
switched capacitor converter, reversion current, non-overlapped rotational-interleaving, dc-dc converter |
| 1 | Tamal Das, Pradip Mandal |
Switched-Capacitor Based Buck Converter Design Using Current Limiter. |
J. Low Power Electronics |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | P. Vijaya Sankara Rao, Pradip Mandal, Sunil Sachdev |
High-Speed Low-Current Duobinary Signaling Over Active Terminated Chip-to-Chip Interconnect. |
ISVLSI |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | P. V. Ratna Kumar, Kaushik Bhattacharyya, Tamal Das, Pradip Mandal |
Improvement of power efficiency in switched capacitor DC-DC converter by shoot-through current elimination. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
shoot-through current, switched capacitor converter, time interleaving |
| 1 | S. Krishna Kumar, P. Uday Bhaskar, Santanu Chattopadhyay, Pradip Mandal |
Circuit Partitioning Using Particle Swarm Optimization for Pseudo-Exhaustive Testing. |
ARTCom |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Samiran DasGupta, Pradip Mandal |
An automated design approach for CMOS LDO regulators. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Tamal Das, Pradip Mandal |
Switched-Capacitor Based Buck Converter Design Using Current Limiter for Better Efficiency and Output Ripple. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kaushik Bhattacharyya, Pradip Mandal |
A Low Voltage, Low Ripple, on Chip, Dual Switch-Capacitor Based Hybrid DC-DC Converter. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Saurav Bandyopadhyay, Pradip Mandal, Stephen E. Ralph, Kenneth Pedrotti |
Integrated TIA-Equalizer for High Speed Optical Link. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Kshitij Yadav, Pradip Mandal |
Design and Analysis of a VHF OTA-C Cell for Optimum Phase Response. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | R. G. Raghavendra, Pradip Mandal |
An On-Chip Voltage Regulator with Improved Load Regulation and Light Load Power Efficiency. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashis Maity, R. G. Raghavendra, Pradip Mandal |
On-Chip Voltage Regulator with Improved Transient Response. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | S. S. Prasad, Pradip Mandal |
A single circuit solution for voltage sensors. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Gunjan Mandal, Pradip Mandal |
Low-power LVDS receiver for 1.3Gbps physical layer (PHY) interface. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Debashis Mandal, Pradip Mandal |
High voltage tolerant output buffer design for mixed voltage interfaces. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | S. S. Prasad, Pradip Mandal |
A CMOS Beta Multiplier Voltage Reference with Improved Temperature Performance and Silicon Tunability. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Pradip Mandal |
A Narrow Pulse- Suppressing Filter For Input Buffer. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
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| 1 | Gunjan Mandal, Pradip Mandal |
Low power LVDS transmitter with low common mode variation for 1GB/s-per pin operation. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Pradip Mandal, V. Visvanathan |
CMOS op-amp sizing using a geometric programming formulation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Pradip Mandal, V. Visvanathan |
A New Approach for CMOS Op-Amp Synthesis. |
VLSI Design |
1999 |
DBLP BibTeX RDF |
|
| 1 | Pradip Mandal, V. Visvanathan |
A Self-Biased High Performance Folded Cascode CMOS Op-Amp. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Pradip Mandal, V. Visvanathan |
Design of high performance two stage CMOS cascode op-amps with stable biasing. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
two stage CMOS cascode op-amps, stable biasing, mirror biasing, output voltage, bias variations, low frequency common mode rejection ratios, power supply rejection ratios, systematic offset, circuit analysis computing, performance metrics, integrated circuit design, circuit simulations, operational amplifiers, CMOS analogue integrated circuits, slew rate, circuit stability |
| 1 | Pradip Mandal, V. Visvanathan |
Macromodeling of the A.C. characteristics of CMOS Op-amps. |
ICCAD |
1993 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #37 of 37 (100 per page; Change: )
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