Search results for "Pranav Ashar"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Pranav Ashar	Clock domain verification challenges and scalable solutions.	HLDVT	2010	DBLP DOI BibTeX RDF
1	Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Pranav Ashar	Efficient SAT-based bounded model checking for software verification.	Theor. Comput. Sci.	2008	DBLP DOI BibTeX RDF
1	Aleksandr Zaks, Zijiang Yang, Ilya Shlyakhter, Franjo Ivancic, Srihari Cadambi, Malay K. Ganai, Aarti Gupta, Pranav Ashar	Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Aarti Gupta, Pranav Ashar	Verification of Embedded Memory Systems using Efficient Memory Modeling	CoRR	2007	DBLP BibTeX RDF
1	Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar	Efficient distributed SAT and SAT-based distributed Bounded Model Checking.	STTT	2006	DBLP DOI BibTeX RDF	Distributed-SAT, Parallel SAT, Model Checking, Formal Verification, SAT, BMC
1	Malay K. Ganai, Aarti Gupta, Pranav Ashar	DiVer: SAT-Based Model Checking Platform for Verifying Large Scale Systems.	TACAS	2005	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Aarti Gupta, Pranav Ashar	Beyond safety: customized SAT-based model checking.	DAC	2005	DBLP DOI BibTeX RDF	circuit cofactoring, unbounded model checking, formal verification, SAT, liveness, bounded model checking, LTL
1	Aarti Gupta, Malay K. Ganai, Pranav Ashar	Lazy Constraints and SAT Heuristics for Proof-Based Abstraction.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Aarti Gupta, Pranav Ashar	Verification of Embedded Memory Systems using Efficient Memory Modeling.	DATE	2005	DBLP DOI BibTeX RDF
1	Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Ilya Shlyakhter, Pranav Ashar	F-Soft: Software Verification Platform.	CAV	2005	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Aarti Gupta, Pranav Ashar	Efficient Modeling of Embedded Memories in Bounded Model Checking.	CAV	2004	DBLP DOI BibTeX RDF
1	Pranav Ashar, Malay K. Ganai, Aarti Gupta, Franjo Ivancic, Zijiang Yang	Efficient SAT-based Bounded Model Checking for Software Verification.	ISoLA (Preliminary proceedings)	2004	DBLP BibTeX RDF
1	Malay K. Ganai, Aarti Gupta, Pranav Ashar	Efficient SAT-based unbounded symbolic model checking using circuit cofactoring.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar	Learning from BDDs in SAT-based bounded model checking.	DAC	2003	DBLP DOI BibTeX RDF	BDD learning, learning, SAT, BDDs, bounded model checking, boolean satisfiability, SAT solvers, property checking
1	Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar	Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking.	CHARME	2003	DBLP DOI BibTeX RDF
1	Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar	Abstraction and BDDs Complement SAT-Based BMC in DiVer.	CAV	2003	DBLP DOI BibTeX RDF
1	Aarti Gupta, Malay K. Ganai, Zijiang Yang, Pranav Ashar	Iterative Abstraction using SAT-based BMC with Proof Analysis.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Farzan Fallah, Pranav Ashar, Srinivas Devadas	Functional vector generation for sequential HDL models under an observability-based code coverage metric.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Srihari Cadambi, Chandra Mulpuri, Pranav Ashar	A fast, inexpensive and scalable hardware acceleration technique for functional simulation.	DAC	2002	DBLP DOI BibTeX RDF	FPGA, hardware acceleration, VLIW, functional simulation
1	Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik	Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver.	DAC	2002	DBLP DOI BibTeX RDF	boolean constraint propagation (BCP), bounded model checking (BMC), conjunctive normal form (CNF), boolean satisfiability (SAT)
1	Aarti Gupta, Albert E. Casavant, Pranav Ashar, X. G. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi	Property-Specific Testbench Generation for Guided Simulation.	VLSI Design	2002	DBLP DOI BibTeX RDF	guided simulation, intelligent testbench generation, witness graph, property-specific testbench, approximate model checking, symbolic model checking, iterative refinement
1	Pranav Ashar, Aarti Gupta, Sharad Malik	Using complete-1-distinguishability for FSM equivalence checking.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	Bisimulation relation, complete-1-distinguishability, finite state machine equivalence, sequential logic synthesis, equivalence checking
1	Aarti Gupta, Anubhav Gupta, Zijiang Yang, Pranav Ashar	Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation.	DAC	2001	DBLP DOI BibTeX RDF
1	Albert E. Casavant, Aarti Gupta, S. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi, Pranav Ashar	Property-specific witness graph generation for guided simulation.	DATE	2001	DBLP DOI BibTeX RDF
1	Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, Sharad Malik	Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs.	ICCAD	2001	DBLP BibTeX RDF
1	Aarti Gupta, Zijiang Yang, Pranav Ashar, Anubhav Gupta	SAT-Based Image Computation with Application in Reachability Analysis.	FMCAD	2000	DBLP DOI BibTeX RDF
1	Aarti Gupta, Pranav Ashar	Fast Error Diagnosis for Combinational Verification.	VLSI Design	2000	DBLP DOI BibTeX RDF	Satisfiability Checking, Formal Verification, Combinational Circuits, Binary Decision Diagrams, Logic Simulation, Error Diagnosis
1	Yang Xia, Pranav Ashar	Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration Architecture.	VLSI Design	2000	DBLP DOI BibTeX RDF	Combinational Loop, Model Checking, Formal Verification, Temporal Logic, Time Division Multiplexing, Token Ring, Computational Tree Logic, Bus Protocol
1	Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik	Using configurable computing to accelerate Boolean satisfiability.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Farzan Fallah, Pranav Ashar, Srinivas Devadas	Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage.	DAC	1999	DBLP DOI BibTeX RDF
1	Aarti Gupta, Pranav Ashar, Sharad Malik	Exploiting Retiming in a Guided Simulation Based Validation Methodology.	CHARME	1999	DBLP DOI BibTeX RDF
1	Zhen Luo, Margaret Martonosi, Pranav Ashar	An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking.	FCCM	1999	DBLP DOI BibTeX RDF	Scanline Algorithm, Configurable Hardware, FPGA, DRC
1	Pranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya	Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation.	ICCD	1999	DBLP DOI BibTeX RDF
1	Vivek Tiwari, Sharad Malik, Pranav Ashar	Guarded evaluation: pushing power management to logic synthesis/design.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
1	Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik	Solving Boolean Satisfiability with Dynamic Hardware Configurations.	FPL	1998	DBLP DOI BibTeX RDF
1	Peixin Zhong, Pranav Ashar, Sharad Malik, Margaret Martonosi	Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability.	DAC	1998	DBLP DOI BibTeX RDF	reconstruction, emulation, visibility, functional simulation
1	Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik	Accelerating Boolean Satisfiability with Configurable Hardware. (PDF / PS)	FCCM	1998	DBLP DOI BibTeX RDF
1	Aarti Gupta, Pranav Ashar	Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking.	VLSI Design	1998	DBLP DOI BibTeX RDF	ATPG techniques, circuit similarity, formal verification, combinational circuits, Boolean satisfiability (SAT), combinational equivalence checking, Binary Decision Diagrams (BDDs)
1	Pranav Ashar, Subhrajit Bhattacharya, Anand Raghunathan, Akira Mukaiyama	Verification of RTL generated from scheduled behavior in a high-level synthesis flow.	ICCAD	1998	DBLP DOI BibTeX RDF
1	Aarti Gupta, Sharad Malik, Pranav Ashar	Toward Formalizing a Validation Methodology Using Simulation Coverage.	DAC	1997	DBLP DOI BibTeX RDF
1	Vivek Tiwari, Pranav Ashar, Sharad Malik	Technology mapping for low power in logic synthesis.	Integration	1996	DBLP DOI BibTeX RDF
1	José Monteiro, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar	Scheduling Techniques to Enable Power Management.	DAC	1996	DBLP DOI BibTeX RDF
1	Pranav Ashar, Aarti Gupta, Sharad Malik	Using complete-1-distinguishability for FSM equivalence checking.	ICCAD	1996	DBLP DOI BibTeX RDF	sequential logic synthesis and verification, finite state machine equivalence, bisimulation relation, 1-distinguishability, 1-equivalence, formal verification
1	Anand Raghunathan, Pranav Ashar, Sharad Malik	Test generation for cyclic combinational circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
1	Pranav Ashar, Sujit Dey, Sharad Malik	Exploiting multicycle false paths in the performance optimization of sequential logic circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
1	Pranav Ashar, Sharad Malik	Functional timing analysis using ATPG.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
1	Vivek Tiwari, Sharad Malik, Pranav Ashar	Guarded evaluation: pushing power management to logic synthesis/design.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Anand Raghunathan, Pranav Ashar, Sharad Malik	Test generation for cyclic combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	cyclic combinational circuits, bus structures, single-stuck-at fault test pattern, test generation problem, program RAM, fault diagnosis, logic testing, integrated circuit testing, network topology, combinational circuits, automatic testing, fault coverage, test pattern generators, formal analysis, data paths, testing algorithm, combinational logic circuits, untestable faults
1	Pranav Ashar, Sharad Malik	Fast functional simulation using branching programs.	ICCAD	1995	DBLP DOI BibTeX RDF	compiled code simulation, cycle-based functional simulation, fast functional simulation, functional delay-independent logic simulation, levelized compiled-code, switch level functional simulation, synchronous digital systems, Boolean functions, system design, logic design, logic CAD, decision theory, circuit analysis computing, benchmark circuits, branching programs
1	Pranav Ashar, Sharad Malik	Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications.	DAC	1994	DBLP DOI BibTeX RDF
1	Pranav Ashar, Matthew Cheong	Efficient breadth-first manipulation of binary decision diagrams.	ICCAD	1994	DBLP DOI BibTeX RDF
1	Pranav Ashar, Srinivas Devadas, Kurt Keutzer	Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks.	Formal Methods in System Design	1993	DBLP DOI BibTeX RDF
1	Vivek Tiwari, Pranav Ashar, Sharad Malik	Technology Mapping for Lower Power.	DAC	1993	DBLP DOI BibTeX RDF
1	Pranav Ashar, Sujit Dey, Sharad Malik	Exploiting multi-cycle false paths in the performance optimization of sequential circuits.	ICCAD	1992	DBLP DOI BibTeX RDF
1	Pranav Ashar, Srinivas Devadas, A. Richard Newton	Irredundant interacting sequential machines via optimal logic synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	1991	DBLP DOI BibTeX RDF
1	Pranav Ashar, Srinivas Devadas, A. Richard Newton	Optimum and heuristic algorithms for an approach to finite state machine decomposition.	IEEE Trans. on CAD of Integrated Circuits and Systems	1991	DBLP DOI BibTeX RDF
1	Pranav Ashar, Srinivas Devadas, Kurt Keutzer	Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks.	ITC	1991	DBLP DOI BibTeX RDF
1	Pranav Ashar, Abhijit Ghosh, Srinivas Devadas	Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams.	ICCD	1991	DBLP BibTeX RDF
1	Pranav Ashar, Srinivas Devadas, A. Richard Newton	A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines.	DAC	1990	DBLP DOI BibTeX RDF
1	Pranav Ashar, Abhijit Ghosh, Srinivas Devadas, A. Richard Newton	Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test.	ICCAD	1990	DBLP BibTeX RDF

Publications of "Pranav Ashar" ( http://dblp.L3S.de/Authors/Pranav_Ashar )