Search results for "Praveen Raghavan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Robert Fasthuber, Min Li, David Novo, Praveen Raghavan, Liesbet Van der Perre, Francky Catthoor	Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors.	Signal Processing Systems	2011	DBLP DOI BibTeX RDF
1	Martin Palkovic, Jeroen Declerck, Praveen Raghavan, Antoine Dejonghe, Liesbet Van der Perre	Dart - a high level software-defined radio platform model for developing the run-time controller.	ICASSP	2011	DBLP DOI BibTeX RDF
1	Prashant Agrawal, Robert Fasthuber, Praveen Raghavan, Tom Vander Aa, Ubaid Ahmad, Liesbet Van der Perre, Francky Catthoor	High level analysis of trade-offs across different partitioning schemes for wireless applications.	SiPS	2011	DBLP DOI BibTeX RDF
1	Nikolaos Zompakis, Antonis Papanikolaou, Praveen Raghavan, Dimitrios Soudris, Francky Catthoor	Enabling efficient system configurations for dynamic wireless baseband engines using system scenarios.	SiPS	2011	DBLP DOI BibTeX RDF
1	Ittetsu Taniguchi, Mitsuya Uchida, Hiroyuki Tomiyama, Masahiro Fukui, Praveen Raghavan, Francky Catthoor	An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating.	DSD	2011	DBLP DOI BibTeX RDF
1	Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Ettore Speziale, Diego Melpignano, J. M. Zins, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Iraklis Anagnostopoulos, Alexandros Bartzas, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Junaid Ansari, Petri Mähönen, Bart Vanthournout	Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach.	ReCoSoC	2011	DBLP DOI BibTeX RDF
1	Bjorn De Sutter, Osman Allam, Praveen Raghavan, Roeland Vandebriel, Hans Cappelle, Tom Vander Aa, Bingfeng Mei	An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors.	Signal Processing Systems	2010	DBLP DOI BibTeX RDF
1	Jeroen Declerck, Praveen Raghavan, Frederik Naessens, Tom Vander Aa, Lieven Hollevoet, Antoine Dejonghe, Liesbet Van der Perre	SDR platform for 802.11n and 3-GPP LTE.	ICSAMOS	2010	DBLP DOI BibTeX RDF
1	Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Andrea Di Biagio, Ettore Speziale, Michele Tartara, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Sotirios Xydis, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout	2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	David Novo, Min Li, Robert Fasthuber, Praveen Raghavan, Francky Catthoor	Exploiting finite precision information to guide data-flow mapping.	DAC	2010	DBLP DOI BibTeX RDF	finite precision, mapping efficiency, ASIP
1	Tom Vander Aa, Praveen Raghavan, Scott A. Mahlke, Bjorn De Sutter, Aviral Shrivastava, Frank Hannig	Compilation techniques for CGRAs: exploring all parallelization approaches.	CODES+ISSS	2010	DBLP DOI BibTeX RDF
1	Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest	EMPIRE: Empirical power/area/timing models for register files.	Microprocessors and Microsystems - Embedded Hardware Design	2009	DBLP DOI BibTeX RDF
1	Javed Absar, Praveen Raghavan, Andy Lambrechts, Min Li, Murali Jayapala, Francky Catthoor	Locality optimization in a compiler for wireless applications.	Design Autom. for Emb. Sys.	2009	DBLP DOI BibTeX RDF
1	Ittetsu Taniguchi, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Yoshinori Takeuchi, Masaharu Imai	Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Praveen Raghavan, Murali Jayapala, Andy Lambrechts, Javed Absar, Francky Catthoor	Playing the trade-off game: Architecture exploration using Coffeee.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	design, embedded systems, Energy, VLIW, processors, power estimation, loop transformations, architecture exploration, area, power-performance trade-off, compiler-architecture interaction
1	Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest	Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
1	Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Bingfeng Mei, Francky Catthoor, Diederik Verkest	Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Robert Fasthuber, Min Li, David Novo, Praveen Raghavan, Liesbet Van der Perre, Francky Catthoor	Novel energy-efficient scalable soft-output SSFE MIMO detector architectures.	ICSAMOS	2009	DBLP DOI BibTeX RDF
1	David Novo, Robert Fasthuber, Praveen Raghavan, André Bourdoux, Min Li, Liesbet Van der Perre, Francky Catthoor	Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS.	SiPS	2009	DBLP DOI BibTeX RDF
1	Praveen Raghavan, Francky Catthoor	Register file exploration for a multi-standard wireless forward error correction ASIP.	SiPS	2009	DBLP DOI BibTeX RDF
1	Nikolas Kroupis, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Dimitrios Soudris	Compilation Technique for Loop Overhead Minimization.	DSD	2009	DBLP DOI BibTeX RDF
1	Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Praveen Raghavan, Francky Catthoor	SARA: StreAm register allocation.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	stream register, low power, register allocation, spatial locality
1	Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai	Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	David Atienza, Praveen Raghavan, José Luis Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo	Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures.	Integration	2008	DBLP DOI BibTeX RDF
1	Frederik Naessens, Bruno Bougard, Siebert Bressinck, Lieven Hollevoet, Praveen Raghavan, Liesbet Van der Perre, Francky Catthoor	A unified instruction set programmable architecture for multi-standard advanced forward error correction.	SiPS	2008	DBLP DOI BibTeX RDF
1	Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai	Operation shuffling over cycle boundaries for low energy L0 clustering.	ASAP	2008	DBLP DOI BibTeX RDF
1	Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Diederik Verkest	Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor.	VLSI Design	2008	DBLP DOI BibTeX RDF	Interconnect-Aware Design, Low Power, Processor Architecture, Energy-Aware Design
1	Praveen Raghavan, Andy Lambrechts, Javed Absar, Murali Jayapala, Francky Catthoor, Diederik Verkest	Coffee: COmpiler Framework for Energy-Aware Exploration.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai	Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Compilers for low energy, loop buffers, VLIW processors
1	José L. Ayala, Marisa López-Vallejo, David Atienza, Praveen Raghavan, Francky Catthoor, Diederik Verkest	Energy-aware compilation and hardware design for VLIW embedded systems.	IJES	2007	DBLP DOI BibTeX RDF
1	Thomas Schuster, Bruno Bougard, Praveen Raghavan, Robert Priewasser, David Novo, Liesbet Van der Perre, Francky Catthoor	Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals.	SAMOS	2007	DBLP DOI BibTeX RDF
1	Praveen Raghavan, Nandhavel Sethubalasubramanian, Satyakiran Munaga, Estela Rey Ramos, Murali Jayapala, Oliver Weiss, Francky Catthoor, Diederik Verkest	Semi Custom Design: A Case Study on SIMD Shufflers.	PATMOS	2007	DBLP DOI BibTeX RDF
1	Praveen Raghavan, Satyakiran Munaga, Estela Rey Ramos, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest	A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors.	ARCS	2007	DBLP DOI BibTeX RDF
1	Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Henk Corporaal	Very wide register: an asymmetric register file organization for low power embedded processors.	DATE	2007	DBLP DOI BibTeX RDF
1	Praveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo	Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Javed Absar, Min Li, Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Arnout Vandecappelle, Francky Catthoor	Locality optimization in wireless applications.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	access, reuse, layout, spatial, temporal, loop-nest
1	Daniele Paolo Scarpazza, Praveen Raghavan, David Novo, Francky Catthoor, Diederik Verkest	Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism.	PATMOS	2006	DBLP DOI BibTeX RDF
1	David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo	Compiler-Driven Leakage Energy Reduction in Banked Register Files.	PATMOS	2006	DBLP DOI BibTeX RDF
1	Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest	Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors.	DATE	2006	DBLP DOI BibTeX RDF
1	Andy Lambrechts, Praveen Raghavan, Anthony Leroy, Guillermo Talavera, Tom Vander Aa, Murali Jayapala, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina	Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application.	ASAP	2005	DBLP DOI BibTeX RDF
1	Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai	Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors.	ESTImedia	2005	DBLP DOI BibTeX RDF

Publications of "Praveen Raghavan" ( http://dblp.L3S.de/Authors/Praveen_Raghavan )