| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Preeti Ranjan Panda, M. Balakrishnan, Anant Vishnoi |
Compressing Cache State for Postsilicon Processor Debug.  |
IEEE Trans. Computers  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda |
A SysML Profile for Development and Early Validation of TLM 2.0 Models. |
ECMFA |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda |
A UML based framework for efficient validation of TLM 2 models. |
FDL |
2011 |
DBLP BibTeX RDF |
|
| 1 | Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar |
Exploiting temporal decoupling to accelerate trace-driven NoC emulation. |
CODES+ISSS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Preeti Ranjan Panda, Rajendran Panda |
Guest Editorial: Special Issue on VLSI Design and Embedded Systems. |
International Journal of Parallel Programming |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Preeti Ranjan Panda, Anant Vishnoi, M. Balakrishnan |
Enhancing post-silicon processor debug with Incremental Cache state Dumping. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Anshul Kumar, Preeti Ranjan Panda |
Front-End Design Flows for Systems on Chip: An Embedded Tutorial. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
SoC Platform, Simulation, Prototyping, ASIPs, Design flow, Communication Architecture |
| 1 | B. V. N. Silpa, Gummidipudi Krishnaiah, Preeti Ranjan Panda |
Rank based dynamic voltage and frequency scaling fortiled graphics processors. |
CODES+ISSS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar |
FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulation. |
CODES+ISSS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajendran Panda, Preeti Ranjan Panda |
A Special Issue on the "22nd IEEE International Conference on VLSI Design" New Delhi, India, 5-9 January 2009. |
J. Low Power Electronics |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | B. V. N. Silpa, Kumar S. S. Vemuri, Preeti Ranjan Panda |
Adaptive Partitioning of Vertex Shader for Low Power High Performance Geometry Engine. |
ISVC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan |
Online cache state dumping for processor debug. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
cache compression, processor debug, silicon debug, design for debug, post-silicon validation |
| 1 | Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan |
Cache aware compression for processor debug support. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Aryabartta Sahu, M. Balakrishnan, Preeti Ranjan Panda |
A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Preeti Ranjan Panda |
Guest Editor Introduction: Special Issue on Multiprocessor-based Embedded Systems. |
International Journal of Parallel Programming |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Pushkar Tripathi, Rohan Jain, Srikanth Kurra, Preeti Ranjan Panda |
REWIRED - Register Write Inhibition by Resource Dedication. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | B. V. N. Silpa, Anjul Patney, Tushar Krishna, Preeti Ranjan Panda, G. S. Visweswaran |
Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar |
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. |
International Journal of Parallel Programming |
2007 |
DBLP DOI BibTeX RDF |
Performance evaluation, VLIW, ASIP, Clustered VLIW processors |
| 1 | Rahul Jain, Preeti Ranjan Panda |
Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda |
Customization of Register File Banking Architecture for Low Power. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda |
Power Reduction in VLIW Processor with Compiler Driven Bypass Network. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Srikanth Kurra, Neeraj Kumar Singh, Preeti Ranjan Panda |
The impact of loop unrolling on controller delay in high level synthesis. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Rahul Jain, Preeti Ranjan Panda |
An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda |
Rapid estimation of control delay from high-level specifications. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
control delay, high level synthesis, estimation, FSM |
| 1 | Preeti Ranjan Panda |
Abridged addressing: a low power memory addressing strategy. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Vikram Singh Saun, Preeti Ranjan Panda |
Extracting Exact Finite State Machines from Behavioral SystemC Descriptions. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar |
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda |
Memory allocation and mapping in high-level synthesis - an integrated approach. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ramesh Chandra, Preeti Ranjan Panda, Jörg Henkel, Sri Parameswaran, Loganath Ramachandran |
Specification and Design of Multi-Million Gate SOCs. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Preeti Ranjan Panda, Nikil D. Dutt |
Memory Architectures for Embedded Systems-On-Chip. |
HiPC |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda |
An integrated algorithm for memory allocation and assignment in high-level synthesis. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
memory assignemt, scheduling effect, memory allocation, memory design |
| 1 | Preeti Ranjan Panda, Lakshmikantam Chitturi |
An energy-conscious algorithm for memory port allocation. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Preeti Ranjan Panda, Francky Catthoor, Nikil D. Dutt, Koen Danckaert, Erik Brockmeyer, Chidamber Kulkarni, Arnout Vandecappelle, Per Gunnar Kjeldsberg |
Data and memory optimization techniques for embedded systems. |
ACM Trans. Design Autom. Electr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
data optimization, memory architecture customization, memory power dissipation, high-level synthesis, survey, SRAM, allocation, data cache, DRAM, register file, architecture exploration, code transformation, address generation, size estimation |
| 1 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau, Francky Catthoor, Arnout Vandecappelle, Erik Brockmeyer, Chidamber Kulkarni, Eddy de Greef |
Data Memory Organization and Optimizations in Application-Specific Systems. |
IEEE Design & Test of Computers |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Preeti Ranjan Panda |
SystemC. |
ISSS |
2001 |
DBLP BibTeX RDF |
|
| 1 | Preeti Ranjan Panda, Luc Séméria, Giovanni De Micheli |
Cache-efficient memory layout of aggregate data structures. |
ISSS |
2001 |
DBLP BibTeX RDF |
|
| 1 | Wolfgang Rosenstiel, Brian Bailey, Masahiro Fujita, Guang R. Gao, Rajesh K. Gupta, Preeti Ranjan Panda |
New design paradigms. |
ISSS |
2001 |
DBLP BibTeX RDF |
|
| 1 | Doris Keitel-Schulz, Norbert Wehn, Francky Catthoor, Preeti Ranjan Panda |
Embedded Memories in System Design: Technology, Application, Design and Tools. |
VLSI Design |
2001 |
DBLP BibTeX RDF |
|
| 1 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems. |
ACM Trans. Design Autom. Electr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
system design, data cache, data partitioning, system synthesis, scratch-pad memory, on-chip memory, memory synthesis |
| 1 | Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau |
Augmenting Loop Tiling with Data Alignment for Improved Cache Performance. |
IEEE Trans. Computers |
1999 |
DBLP DOI BibTeX RDF |
data cache, Loop tiling, data alignment, cache conflict |
| 1 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
Local memory exploration and optimization in embedded systems. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Preeti Ranjan Panda, Nikil D. Dutt |
Low-power memory mapping through reducing address bus activity. |
IEEE Trans. VLSI Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Preeti Ranjan Panda |
Memory bank customization and assignment in behavioral synthesis. |
ICCAD |
1999 |
DBLP BibTeX RDF |
|
| 1 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
Incorporating DRAM access modes into high-level synthesis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
Data Cache Sizing for Embedded Processor Applications. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
Memory data organization for improved cache performance in embedded processor applications. |
ACM Trans. Design Autom. Electr. Syst. |
1997 |
DBLP DOI BibTeX RDF |
system design, cache memory, data cache, system synthesis, memory synthesis |
| 1 | Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau |
Improving cache Performance Through Tiling and Data Alignment. |
IRREGULAR |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
Architectural Exploration and Optimization of Local Memory in Embedded Systems. (PDF / PS) |
ISSS |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Preeti Ranjan Panda, Nikil D. Dutt |
Behavioral Array Mapping into Multiport Memories Targeting Low Power. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
Efficient utilization of scratch-pad memory in embedded processor applications. |
ED&TC |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
Exploiting off-chip memory access modes in high-level synthesis. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
High Level Synthesis, DRAM, Memory Synthesis |
| 1 | Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau |
A Data Alignment Technique for Improving Cache Performance. |
ICCD |
1997 |
DBLP BibTeX RDF |
|
| 1 | Preeti Ranjan Panda, Nikil D. Dutt |
Low-power mapping of behavioral arrays to multiple memories. |
ISLPED |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
Memory Organization for Improved Data Cache Performance in Embedded Processors. (PDF / PS) |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Preeti Ranjan Panda, Nikil D. Dutt |
1995 high level synthesis design repository. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
1995 high level synthesis design repository, VHDL language, behavioral finite state machines, behavioral level, computational complexity, high level synthesis, finite state machines, VHDL, microprocessors, hardware description languages, microprocessor chips, floating point units |
| 1 | Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri |
Estimating the Complexity of Synthesized Designs from FSM Specifications. |
IEEE Design & Test of Computers |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri |
A Flexible Scheme for State Assignment Based on Characteristics of the FSM. |
ICCAD |
1991 |
DBLP BibTeX RDF |
|
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