Search results for "Process Variability"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Gustavo Neuberger, Gilson I. Wirth, Ricardo Reis	Protecting digital circuits against hold time violation due to process variability.	SBCCI	2009	DBLP DOI BibTeX RDF	flip-flop characterization, hold time violations, race immunity, clock skew, process variability
3	Victoria Wang, Kanak Agarwal, Sani R. Nassif, Kevin J. Nowka, Dejan Markovic	A Design Model for Random Process Variability.	ISQED	2008	DBLP DOI BibTeX RDF	random process variability, current variation, modeling, principal component analysis
3	Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, Daniel J. Sorin	Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	microarchitecture, process variability
3	Antonis Papanikolaou, F. Lobmaier, Hua Wang, Miguel Miranda, Francky Catthoor	A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	system-level compensation, process variability, parametric yield
2	Samar K. Saha	Modeling Process Variability in Scaled CMOS Technology.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	compact variability modeling, gate-oxide thickness variability, high-k dielectric, line-edge roughness, polysilicon granularity, random discrete dopants, scaled CMOS technology, statistical compact modeling, design and test, process variability, metal gate
2	Victoria Wang, Dejan Markovic	Linear analysis of random process variability.	ICCAD	2008	DBLP DOI BibTeX RDF
2	Bogdan F. Romanescu, Michael E. Bauer, Daniel J. Sorin, Sule Ozev	Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation.	PACT	2007	DBLP DOI BibTeX RDF
2	Bernard J. Schroer, Gregory A. Harris, Dietmar P. F. Möller	Simulation to evaluate several critical factors effecting manufacturing.	SCSC	2007	DBLP DOI BibTeX RDF	lean manufacturing, vendor-managed inventory, discrete event simulation, process variability, Kanban
2	Concepción Sanz, Manuel Prieto, Antonis Papanikolaou, Miguel Miranda, Francky Catthoor	System-level process variability compensation on memory organizations of dynamic applications: a case study.	ISQED	2006	DBLP DOI BibTeX RDF
2	Hua Wang, Miguel Miranda, Francky Catthoor, Wim Dehaene	On the Combined Impact of Soft and Medium Gate Oxide Breakdown and Process Variability on the Parametric Figures of SRAM components.	MTDT	2006	DBLP DOI BibTeX RDF
2	Antonis Papanikolaou, T. Grabner, Miguel Miranda, Philippe Roussel, Francky Catthoor	Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	system exploration, process variability, parametric yield
2	Fang Liu, Sule Ozev	Fast Hierarchical Process Variability Analysis and Parametric Test Development for Analog/RF Circuits.	ICCD	2005	DBLP DOI BibTeX RDF
1	Tetsuya Iizuka, Kunihiro Asada	All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator.	IEICE Transactions	2012	DBLP BibTeX RDF
1	Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada	All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Zhiyuan Hu, Zhangli Liu, Hua Shao, Zhengxuan Zhang, Bingxu Ning, Ming Chen, Dawei Bi, Shichang Zou	Impact of within-wafer process variability on radiation response.	Microelectronics Journal	2011	DBLP DOI BibTeX RDF
1	Stefano Stanzione, Daniele Puntin, Giuseppe Iannaccone	CMOS Silicon Physical Unclonable Functions Based on Intrinsic Process Variability.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Tomás Martínez-Ruiz, Félix García, Mario Piattini, Jürgen Münch	Modelling software process variability: an empirical study.	IET Software	2011	DBLP DOI BibTeX RDF
1	Peter Maxwell	Adaptive Testing: Dealing with Process Variability.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF
1	Matthias Weidlich, Jan Mendling, Mathias Weske	A Foundational Approach for Managing Process Variability.	CAiSE	2011	DBLP DOI BibTeX RDF
1	Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada	All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Tetsuya Iizuka, Kunihiro Asada	An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator.	DDECS	2011	DBLP DOI BibTeX RDF
1	Shamshuritawati Sharif, Maman A. Djauhari	An application of network topology to understand the signal in process variability: A case study in petrochemical industry.	IEEM	2011	DBLP DOI BibTeX RDF
1	Kyarash Shahriari, Feng Ding	Process variability and inherent efficiency enhancement in industrial processes: Two case studies in pulp and paper industry.	CCA	2011	DBLP DOI BibTeX RDF
1	Nabila Moubdi, Philippe Maurine, Robin Wilson, Sylvain Engels, Nadine Azémard, Vincent Dumettier, Pierre Busson	On-Chip Process Variability Monitoring Flow.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	S. Du, J. Lv, L. Xi	An integrated system for on-line intelligent monitoring and identifying process variability and its application.	Int. J. Computer Integrated Manufacturing	2010	DBLP DOI BibTeX RDF
1	Peter Y. K. Cheung	Process Variability and Degradation: New Frontier for Reconfigurable.	ARC	2010	DBLP DOI BibTeX RDF
1	Tetsuya Iizuka, Toru Nakura, Kunihiro Asada	Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects.	DDECS	2010	DBLP DOI BibTeX RDF
1	Paul Zuber, Petr Dobrovolný, Miguel Miranda	A holistic approach for statistical SRAM analysis.	DAC	2010	DBLP DOI BibTeX RDF	statistical SRAM analysis, process variability, yield prediction
1	Yu Cao, Frank Liu	Guest Editors' Introduction: Compact Variability Modeling in Scaled CMOS Design.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	modeling, process variability
1	Alyssa Bonnoit, Lawrence T. Pileggi	Reducing variability in chip-multiprocessors with adaptive body biasing.	ISLPED	2010	DBLP DOI BibTeX RDF	dynamic voltage/frequency scaling, body biasing
1	Yuan Xie, Yibo Chen	Statistical High-Level Synthesis under Process Variability.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Carles Hernández, Federico Silla, Vicente Santonja, José Duato	A new mechanism to deal with process variability in NoC links.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Concepción Sanz, Manuel Prieto, José Ignacio Gómez, Antonis Papanikolaou, Francky Catthoor	System-level process variability compensation on memory organizations: on the scalability of multi-mode memories.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Siddharth Garg, Diana Marculescu	System-level process variability analysis and mitigation for 3D MPSoCs.	DATE	2009	DBLP BibTeX RDF
1	Yibo Chen, Yuan Xie	Tolerating process variations in high-level synthesis using transparent latches.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Jungseob Lee, Nam Sung Kim	Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating.	DAC	2009	DBLP DOI BibTeX RDF	multicore processor, DVFS, power gating
1	Sari Onaissi, Khaled R. Heloue, Farid N. Najm	Clock skew optimization via wiresizing for timing sign-off covering all process corners.	DAC	2009	DBLP DOI BibTeX RDF	clock skew optimization, parameterized timing analysis, sign-off, wiresizing, variability
1	Andrzej J. Strojwas, Tejas Jhaveri, Vyacheslav Rovner, Lawrence T. Pileggi	Creating an affordable 22nm node using design-lithography co-optimization.	DAC	2009	DBLP DOI BibTeX RDF	design technology co-optimization, templates, DFM, regular fabric
1	Wan-Yu Lee, Iris Hui-Ru Jiang	VIFI-CMP: variability-tolerant chip-multiprocessors for throughput and power.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	chip-multiprocessor, process variation, monte carlo analysis
1	Alyssa Bonnoit, Sebastian Herbert, Diana Marculescu, Lawrence T. Pileggi	Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection.	ISLPED	2009	DBLP DOI BibTeX RDF	dynamic voltage / frequency scaling, body biasing
1	Chun-Yu Chuang, Wai-Kei Mak	Accurate closed-form parameterized block-based statistical timing analysis applying skew-normal distribution.	ISQED	2009	DBLP DOI BibTeX RDF
1	Muhammad Mudassar Nisar, Abhijit Chatterjee	Environment and Process Adaptive Low Power Wireless Baseband Signal Processing Using Dual Real-Time Feedback.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks	Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability.	IEEE Micro	2008	DBLP DOI BibTeX RDF	caches, process variation, variability, dynamic memory
1	Srinivasa R. S. T. G, Jandhyala Srivatsava, Narahari Tondamuthuru R	Process Variability Analysis in DSM Through Statistical Simulations and its Implications to Design Methodologies.	ISQED	2008	DBLP DOI BibTeX RDF	Design Methodologies, Random, DSM, Variations, Systematic
1	Natasa Miskov-Zivanov, Kai-Chiang Wu, Diana Marculescu	Process variability-aware transient fault modeling and analysis.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Sebastian Herbert, Diana Marculescu	Characterizing chip-multiprocessor variability-tolerance.	DAC	2008	DBLP DOI BibTeX RDF	frequency islands, chip-multiprocessor, process variability
1	Qing Yao, Jing Zhang, Haiyang Wang	Business Process-Oriented Software Architecture for Supporting Business Process Change.	ISECS	2008	DBLP DOI BibTeX RDF	SOA, Software Architecture, Configuration, Business Process Management, Process Variability
1	Shreyas Sen, Vishwanath Natarajan, Rajarajan Senguttuvan, Abhijit Chatterjee	Pro-VIZOR: process tunable virtually zero margin low power adaptive RF for wireless systems.	DAC	2008	DBLP DOI BibTeX RDF	low power RF transceivers, process tolerant adaptive RF
1	Concepción Sanz, Manuel Prieto, José Ignacio Gómez, Antonis Papanikolaou, Miguel Miranda, Francky Catthoor	Combining system scenarios and configurable memories to tolerate unpredictability.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	variability compensation, Process variation, parametric yield
1	Bastien Giraud, Amara Amara	Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS.	DELTA	2008	DBLP DOI BibTeX RDF	SRAM cell, Double Gate (DG), Static Noise Margin (SNM), Write Margin (WM)
1	Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung	Fault tolerant methods for reliability in FPGAs.	FPL	2008	DBLP DOI BibTeX RDF
1	Padma Apparao, Ravi R. Iyer, Donald Newell	Implications of cache asymmetry on server consolidation performance.	IISWC	2008	DBLP DOI BibTeX RDF
1	Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang, Alexander Taubin, Mark G. Karpovsky	Asynchronous balanced gates tolerant to interconnect variability.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Patrick Schaumont, David D. Hwang	Turning liabilities into assets: Exploiting deep submicron CMOS technology to design secure embedded circuits.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Young-Gu Kim, Soo-Hwan Kim, Hoon Lim, Sanghoon Lee, Keun-Ho Lee, Young-Kwan Park, Moon-Hyun Yoo	The Statistical Failure Analysis for the Design of Robust SRAM in Nano-Scale Era.	ISQED	2008	DBLP DOI BibTeX RDF	Statistical failure analysis, DFM, SRAM
1	Baker Mohammad, Martin Saint-Laurent, Paul Bassett, Jacob A. Abraham	Cache Design for Low Power and High Yield.	ISQED	2008	DBLP DOI BibTeX RDF	reduce voltage swing, sram yield, SRAM 6T cell, cache design, parametric failure
1	Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas	Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects.	ISQED	2008	DBLP DOI BibTeX RDF	bus coding, delay, process variation
1	Javid Jaffari, Mohab Anis	Statistical Thermal Profile Considering Process Variations: Analysis and Applications.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Ove Armbrust, Masafumi Katahira, Yuko Miyamoto, Jürgen Münch, Haruka Nakao, Alexis Ocampo	Scoping Software Process Models - Initial Concepts and Experience from Defining Space Standards.	ICSP	2008	DBLP DOI BibTeX RDF
1	Mahmoud El-Banna, Dimitar Filev, Ratna Babu Chinnam	Automotive Manufacturing: Intelligent Resistance Welding.	Computational Intelligence in Automotive Applications	2008	DBLP DOI BibTeX RDF
1	Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, Daniel J. Sorin	VariaSim: simulating circuits and systems in the presence of process variability.	SIGARCH Computer Architecture News	2007	DBLP DOI BibTeX RDF
1	Davide Pandini	Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies.	PATMOS	2007	DBLP DOI BibTeX RDF
1	B. P. Harish, Navakanta Bhat, Mahesh B. Patil	Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs.	ICCTA	2007	DBLP DOI BibTeX RDF	mixed-mode simulations, hybrid model, Least Squares Method, Response Surface Methodology
1	Nikolaos Minas, David Kinniment, Keith Heron, Gordon Russell	A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Praveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo	Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Asha Balijepalli, Saurabh Sinha, Yu Cao	Compact modeling of carbon nanotube transistor for early stage process-design exploration.	ISLPED	2007	DBLP DOI BibTeX RDF	optimum delay, schottky-barrier, surface potential, modeling, process variability, CNT
1	Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee	Prospect of ballistic CNFET in high performance applications: Modeling and analysis.	JETC	2007	DBLP DOI BibTeX RDF	Ballistic carbon nanotube FET (CNFET), circuit compatible model, parasitic capacitance, process variability, circuit performance
1	Wei Dong, Zhuo Feng, Peng Li	Efficient VCO phase macromodel generation considering statistical parametric variations.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Zhuo Feng, Peng Li	A methodology for timing model characterization for statistical static timing analysis.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Alexander V. Mitev, Michael Marefat, Dongsheng Ma, Janet Meiling Wang	Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan	Voltage drop reduction for on-chip power delivery considering leakage current variations.	ICCD	2007	DBLP DOI BibTeX RDF
1	Bastien Giraud, Amara Amara, Andrei Vladimirescu	A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo A. L. Reis	Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Maryam Ashouei, Muhammad Mudassar Nisar, Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril	Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Smita Krishnaswamy, Igor L. Markov, John P. Hayes	Tracking Uncertainty with Probabilistic Logic Circuit Testing.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	probabilistic faults, logic circuit testing, fault-modeling framework, test-vector sensitivity, integer linear programming
1	Heiko Thimm, Kathrin Thimm	Explorative Configuration of Supplier Cooperation as an E-Marketplace Service.	CONFENIS	2007	DBLP DOI BibTeX RDF	Internet business collaboration, Inter-organizational enterprise systems, E-Commerce, Electronic marketplace
1	Michael Zapf, Ute Lindheimer, Armin Heinzl	The myth of accelerating business processes through parallel job designs.	Inf. Syst. E-Business Management	2007	DBLP DOI BibTeX RDF	Job parallelization, Order processing, Process simulation, Coordination theory, Business process design, Parallel designs
1	Joonsoo Kim, Michael Orshansky	Towards formal probabilistic power-performance design space exploration.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	formal methodology, hierarchical design exploration, performance, power, probabilistic, canonical representation
1	Kaviraj Chopra, Bo Zhai, David Blaauw, Dennis Sylvester	A new statistical max operation for propagating skewness in statistical timing analysis.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Xiaoyao Liang, David Brooks	Microarchitecture parameter selection to optimize system performance under process variation.	ICCAD	2006	DBLP DOI BibTeX RDF
1	James Donald, Margaret Martonosi	Power efficiency for variation-tolerant multicore processors.	ISLPED	2006	DBLP DOI BibTeX RDF	power, multicore, parallel applications, variation
1	Robert C. Aitken	Reliability Issues for Embedded SRAM at 90nm and Below.	IOLTS	2006	DBLP DOI BibTeX RDF
1	Christopher S. Taillefer, Gordon W. Roberts	Process-insensitive modulated-clock voltage comparator.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Karen Chow	The Challenges and Impact of Parasitic Extraction at 65 nm.	ISQED	2006	DBLP DOI BibTeX RDF
1	Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel	Organic Computing at the System on Chip Level.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Aswath Oruganti, Nagarajan Ranganathan	Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Antonis Papanikolaou, Miguel Miranda, Hua Wang, Francky Catthoor, M. Satyakiran, Pol Marchal, Ben Kaczer, C. Bruynseraede, Zsolt Tokei	Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Fang Liu, Plamen K. Nikolov, Sule Ozev	Parametric Fault Diagnosis for Analog Circuits Using a Bayesian Framework.	VTS	2006	DBLP DOI BibTeX RDF
1	Abhishek Singh, Jim Plusquellic, Dhananjay S. Phatak, Chintan Patel	Defect Simulation Methodology for iDDT Testing.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	iDDT, transient current testing, device testing, ATPG, fault simulation, IDDQ, defect simulation, defect-based test
1	Hua Wang, Miguel Miranda, Wim Dehaene, Francky Catthoor, Karen Maex	Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules.	DATE	2005	DBLP DOI BibTeX RDF
1	Fang Liu, Sule Ozev	Hierarchical analysis of process variation for mixed-signal systems.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Jan M. Rabaey	Design at the end of the silicon roadmap.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	David Blaauw, Kaviraj Chopra	CAD tools for variation tolerance.	DAC	2005	DBLP DOI BibTeX RDF	variability, yield, design flows
1	Diana Marculescu, Emil Talpes	Variability and energy awareness: a microarchitecture-level perspective.	DAC	2005	DBLP DOI BibTeX RDF	GALS design, power consumption, variability
1	Yang Xu, Kan-Lin Hsiung, Xin Li, Ivan Nausieda, Stephen P. Boyd, Lawrence T. Pileggi	OPERA: optimization with ellipsoidal uncertainty for robust analog IC design.	DAC	2005	DBLP DOI BibTeX RDF	optimization, statistical
1	Claire Costello, Owen Molloy, Gerard Lyons, Jim Duggan	Using Event-Based Process Modelling to Support Six Sigma Quality.	DEXA Workshops	2005	DBLP DOI BibTeX RDF
1	Erik Schüler, Luigi Carro	Reliable Digital Circuits Design using Sigma-Delta Modulated Signals.	DFT	2005	DBLP DOI BibTeX RDF
1	Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda	Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture.	ISQED	2005	DBLP DOI BibTeX RDF
1	Farid Boussaïd, Chen Shoushun, Amine Bermak	A Scalable Low Power Imager Architecture for Compound-Eye Vision Sensors.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma	Layout-aware scan chain synthesis for improved path delay fault coverage.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF