Search results for "Processor Architecture"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Sylvain Girbal, Gilles Mouchard, Albert Cohen, Olivier Temam	DiST: a simple, reliable and scalable method to significantly reduce processor architecture simulation time.	SIGMETRICS	2003	DBLP DOI BibTeX RDF	distributed simulation, processor architecture
3	H. Tanaka	Toward more advanced usage of instruction level parallelism by a very large data path processor architecture.	ISPAN	1997	DBLP DOI BibTeX RDF	very large data path processor, instruction analysis, parallel gain, parallel architectures, microprocessor, instruction level parallelism, processor architecture, performance gain
2	Like Yan, Binbin Wu, Yuan Wen, Shaobin Zhang, Tianzhou Chen	A Reconfigurable Processor Architecture Combining Multi-core and Reconfigurable Processing Unit.	CIT	2010	DBLP DOI BibTeX RDF	reconfigurable computing, multi-core, dynamic reconfiguration, processor architecture
2	Satoshi Amamiya, Makoto Amamiya, Ryuzo Hasegawa, Hiroshi Fujita	A continuation-based noninterruptible multithreading processor architecture.	The Journal of Supercomputing	2009	DBLP DOI BibTeX RDF	Parallel processing, Multithreading, Processor architecture, Thread level parallelism, Multithreaded programming
2	Abdulhadi Shoufan, Thorsten Wink, H. Gregor Molter, Sorin A. Huss, Falko Strenzke	A Novel Processor Architecture for McEliece Cryptosystem and FPGA Platforms.	ASAP	2009	DBLP DOI BibTeX RDF
2	Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa	Dual-execution mode processor architecture.	The Journal of Supercomputing	2008	DBLP DOI BibTeX RDF	Dual-execution, Queue computation, Dynamic switching, Hardware usability, Parallel, Embedded core
2	Scott Davidson	How to make your own processor architecture.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF	system-on-chip computing, FPGAs, ASICs, processor architecture, processor design
2	Xing Fang, Dong Wang, Shuming Chen	SPVA: A novel digital signal processor architecture for Software Defined Radio.	AICCSA	2008	DBLP DOI BibTeX RDF
2	Taichi Maekawa, Ben A. Abderazek, Kenichi Kuroda	Single Instruction Dual-Execution Model Processor Architecture.	EUC	2008	DBLP DOI BibTeX RDF
2	Alejandro García, Oliverio J. Santana, Enrique Fernández, Pedro Medina, Mateo Valero	LPA: A First Approach to the Loop Processor Architecture.	HiPEAC	2008	DBLP DOI BibTeX RDF
2	Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Diederik Verkest	Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor.	VLSI Design	2008	DBLP DOI BibTeX RDF	Interconnect-Aware Design, Low Power, Processor Architecture, Energy-Aware Design
2	Mladen Berekovic, Tim Niggemeier	A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	clustering, distributed computing, DSP, MPEG-4, multi-threading, processor architecture, SMT
2	Yong Li 0006, Zhiying Wang, Xue-mi Zhao, Jian Ruan, Kui Dai	Design of a Low-Power Embedded Processor Architecture Using Asynchronous Function Units.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
2	Shorin Kyo, Takuya Koga, Hanno Lieske, Shouhei Nomoto, Shin'ichiro Okazaki	A low-cost mixed-mode parallel processor architecture for embedded systems.	ICS	2007	DBLP DOI BibTeX RDF	embedded systems, parallel architectures, SIMD, MIMD, multimedia processing, tile architectures, mixed-mode
2	Wenjing Rao, Alex Orailoglu, Ramesh Karri	Towards Nanoelectronics Processor Architectures.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	fault tolerance, reliability, computational model, processor architecture, nanoelectronics, time redundancy, hardware redundancy
2	Jim Torresen, Jonas Jakobsen	An FPGA Implemented Processor Architecture with Adaptive Resolution.	AHS	2006	DBLP DOI BibTeX RDF
2	David B. Kirk	Processor architecture: too much parallelism?	PACT	2006	DBLP DOI BibTeX RDF
2	Panagiotis D. Michailidis, Konstantinos G. Margaritis	Implementation of a programmable array processor architecture for approximate string matching algorithms on FPGAs.	IPDPS	2006	DBLP DOI BibTeX RDF
2	Xiaofeng Wu, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger Goodall, Tanya Vladimirova	A Novel Processor Architecture for Real-Time Control.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
2	Zhenghong Wang, Ruby B. Lee	Covert and Side Channels Due to Processor Architecture.	ACSAC	2006	DBLP DOI BibTeX RDF
2	Tsutomu Nishimura, Takuji Miki, Hiroaki Sugiura, Yuki Matsumoto, Masatsugu Kobayashi, Toshiyuki Kato, Tsutomu Eda, Hironori Yamauchi	Configurable multi-processor architecture and its processor element design.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Yongjun Wang, Xiaoming Zhang	A Novel Modeling Method of Network Processor Architecture Based on SystemC.	CIT	2006	DBLP DOI BibTeX RDF
2	In-Pyo Hong, Yong-Joo Lee, Yong-Surk Lee	Next Generation Embedded Processor Architecture for Personal Information Devices.	EUC	2006	DBLP DOI BibTeX RDF
2	Xin Li, Reinhard von Hanxleden	A concurrent reactive Esterel processor based on multi-threading.	SAC	2006	DBLP DOI BibTeX RDF	multithreading, processor architecture, synchronous languages, esterel
2	Mancia Anguita, J. Manuel Martinez-Lechado	MP3 Optimization Exploiting Processor Architecture and using Better Algorithms.	IEEE Micro	2005	DBLP DOI BibTeX RDF	D.3.4.g Optimization, C.1 Processor Architectures, C.1.2.j SIMD processors, E.4.a Data compaction and compression, J.9.c Multimedia applications and multimedia signal processing
2	Masahiro Sowa, Ben A. Abderazek, Tsutomu Yoshinaga	Parallel Queue Processor Architecture Based on Produced Order Computation Model.	The Journal of Supercomputing	2005	DBLP DOI BibTeX RDF	produced order, queue processor, circular queue-registers, design, high performance
2	Claudio Mucci, Fabio Campi, Antonio Deledda, Alberto Fazzi, Mirco Ferri, Massimo Bocchi	A Cycle-Accurate ISS for a Dynamically Reconfigurable Processor Architecture.	IPDPS	2005	DBLP DOI BibTeX RDF
2	Taku Ohsawa, Masamichi Takagi, Shoji Kawahara, Satoshi Matsushita	Pinot: Speculative Multi-threading Processor Architecture Exploiting Parallelism over a Wide Range of Granularities.	MICRO	2005	DBLP DOI BibTeX RDF
2	Hong Yue, Ming-che Lai, Kui Dai, Zhiying Wang	Design of a Configurable Embedded Processor Architecture for DSP Functions.	ICPADS	2005	DBLP DOI BibTeX RDF
2	Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou	A Low-Power Processor Architecture Optimized forWireless Devices.	ASAP	2005	DBLP DOI BibTeX RDF	Pipeline depth, configurable pipeline, power-adaptive processors, Low power, asynchronous circuits
2	Eric Tell, Anders Nilsson, Dake Liu	A Low Area and Low Power Programmable Baseband Processor Architecture.	IWSOC	2005	DBLP DOI BibTeX RDF
2	Janardhan Singaraju, Long Bu, John A. Chandy	A Signature Match Processor Architecture for Network Intrusion Detection.	FCCM	2005	DBLP DOI BibTeX RDF
2	Rafael Dueire Lins	A New Multi-Processor Architecture for Parallel Lazy Cyclic Reference Counting.	SBAC-PAD	2005	DBLP DOI BibTeX RDF
2	Panagiotis D. Michailidis, Konstantinos G. Margaritis	A Programmable Array Processor Architecture for Flexible Approximate String Matching Algorithms.	ICPP Workshops	2005	DBLP DOI BibTeX RDF
2	Ruby B. Lee, A. Murat Fiskiran	PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	multimedia, processor architecture, instruction set architecture, media processing, ISA
2	Matthias Meyer	A Novel Processor Architecture with Exact Tag-Free Pointers.	IEEE Micro	2004	DBLP DOI BibTeX RDF
2	Rainer Buchty, Nevin Heintze, Dino Oliva	Cryptonite - A Programmable Crypto Processor Architecture for High-Bandwidth Applications.	ARCS	2004	DBLP DOI BibTeX RDF
2	Chikafumi Takahashi, Masaaki Kondo, Taisuke Boku, Daisuke Takahashi, Hiroshi Nakamura, Mitsuhisa Sato	SCIMA-SMP: on-chip memory processor architecture for SMP.	WMPI	2004	DBLP DOI BibTeX RDF
2	Frederik Vermeulen, Francky Catthoor, Lode Nachtergaele, Diederik Verkest, Hugo De Man	Power-efficient flexible processor architecture for embedded applications.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
2	Karl-Heinz Zimmermann	A Special Purpose Array Processor Architecture for the Molecular Dynamics Simulation of Point-Mutated Proteins.	VLSI Signal Processing	2003	DBLP DOI BibTeX RDF	point mutation, penicillin amidase, parallel processing, molecular dynamics, protein, array processor
2	Ben A. Abderazek, Soichi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa	On the Design of a Register Queue Based Processor Architecture (FaRM-rq).	ISPA	2003	DBLP DOI BibTeX RDF
2	Konstantinos Sarrigeorgidis, Jan M. Rabaey	Massively Parallel Wireless Reconfigurable Processor Architecture and Programming.	IPDPS	2003	DBLP DOI BibTeX RDF
2	N. Venkateswaran, C. Chandramouli	General Purpose Processor Architecture for Modeling Stochastic Biological Neuronal Assemblies.	ICES	2003	DBLP DOI BibTeX RDF
2	Adronis Niyonkuru, Göran Eggers, Hans Christoph Zeidler	A Reconfigurable Processor Architecture.	FPL	2002	DBLP DOI BibTeX RDF
2	Francisco Rodríguez, José Carlos Campelo, Juan José Serrano	A Watchdog Processor Architecture with Minimal Performance Overhead.	SAFECOMP	2002	DBLP DOI BibTeX RDF
2	Sunghyun Jee, Kannappan Palaniappan	Compiler Processor Tradeoffs for DISVLIW Architecture. (PDF / PS)	ISPAN	2002	DBLP DOI BibTeX RDF	Balanced Scheduling, DISVLIW, Processor architecture, ILP
2	Gerardo Orlando, Christof Paar	A Scalable GF(p) Elliptic Curve Processor Architecture for Programmable Hardware.	CHES	2001	DBLP DOI BibTeX RDF
2	Francky Catthoor, Nikil D. Dutt, Christoforos E. Kozyrakis	How to Solve the Current Memory Access and Data Transfer Bottlenecks: At the Processor Architecture or at the Compiler Level?	DATE	2000	DBLP DOI BibTeX RDF
2	Phillip Stanley-Marbell, Liviu Iftode	Scylla: a smart virtual machine for mobile embedded systems.	WMCSA	2000	DBLP DOI BibTeX RDF	Scylla, smart virtual machine, mobile embedded systems, virtualized processor architecture, inter-device communication, mobile computing, embedded systems, wireless LAN, virtual machines, power management, embedded processors, error recovery, instruction sets, instruction set, prototype system, code mobility, wireless devices
2	Jian Huang, David J. Lilja	An Efficient Strategy for Developing a Simulator for a Novel Concurrent Multithreaded Processor Architecture. (PDF / PS)	MASCOTS	1998	DBLP DOI BibTeX RDF
2	Tsuneo Ikedo, William L. Martens	Multimedia Processor Architecture. (PDF / PS)	ICMCS	1998	DBLP DOI BibTeX RDF
2	Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess	PROPHID: a data-driven multi-processor architecture for high-performance DSP.	ED&TC	1997	DBLP DOI BibTeX RDF
2	Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay S. Parekh, Dean M. Tullsen	Tuning Compiler Optimizations for Simultaneous Multithreading.	MICRO	1997	DBLP BibTeX RDF	cyclic algorithm, fine-grained sharing, inter-thread instruction-level parallelism, loop-iteration scheduling, memory system resources, software speculative execution, performance, parallel programs, parallel architecture, compiler optimizations, shared-memory multiprocessors, processor architecture, instructions, simultaneous multithreading, latency hiding, loop tiling, optimising compilers, inter-processor communication, cache size
2	Thomas Stricker, Thomas R. Gross	Global Address Space, Non-Uniform Bandwidth: A Memory System Performance Characterization of Parallel Systems.	HPCA	1997	DBLP DOI BibTeX RDF	nonuniform bandwidth, memory system performance characterization, local memory accesses, remote write, cost benefit model, DEC Alpha based parallel systems, DEC-Alpha processor architecture, DEC 8400, scalability, compiler, parallel systems, empirical evaluation, memory architecture, coherency, cache storage, access pattern, spatial locality, local memory, global address space, Cray T3E, Cray T3D, clock speed
2	Cheng Chang, Chien-Chung Chen, Yao-Liang Chen, Fu-Shin Huang	Real-time scheduling in a programmable radar signal processor.	RTCSA	1997	DBLP DOI BibTeX RDF	programmable radar signal processor, parallel multi-processor architecture, real-time scheduling algorithm, digital signal processing, real-time scheduling, processing speed, radar signal processing
2	Olivier Thiry, Luc J. M. Claesen	A formal verification technique for embedded software. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	embedded software correctness, assembly program code, CTL temporal logic formulae, embedded system application, assembly language program, formal verification, program verification, formal model, embedded software, processor architecture, instruction set
2	C. J. Elston, D. B. Christianson, P. A. Findlay, G. B. Steven	Hades-towards the design of an asynchronous superscalar processor.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous superscalar processor, Hades, generic processor architecture, asynchronous processor design, decoupled operand forwarding, register writeback, computer architecture, logic design
2	Siamak Arya, Howard Sachs, Sreeram Duvvuru	An architecture for high instruction level parallelism.	HICSS	1995	DBLP DOI BibTeX RDF	high instruction level parallelism, sequential order, code execution, dataflow problems, condition bits, nonblocking cache, Software Scheduled SuperScalar, parallel programming, compiler, parallel architectures, parallel architecture, pipelining, program compilers, data flow analysis, software pipelining, pipeline processing, data flow, processor architecture, speculative execution, control flow, hardware support, branches, program control structures, registers, functional units, multiple instructions, conditional execution
2	John Bunda, Donald S. Fussell, William C. Athas	Energy-efficient instruction set architecture for CMOS microprocessors.	HICSS	1995	DBLP DOI BibTeX RDF	energy-efficient instruction set architecture, CMOS microprocessors, portable battery-based applications, performance-driven designs, processor architecture tradeoffs, program encoding size, instruction set richness, energy cost, speculative instruction fetching, execution resources, instruction-level parallel machines, multiple-path instruction fetching, high execution bandwidth, power management, microprocessor chips, instruction sets, power dissipation, CMOS digital integrated circuits, reduced instruction set computing, cooling, design constraint, instruction delivery, code density
2	Sreeram Duvvuru, Siamak Arya	Evaluation of a branch target address cache.	HICSS	1995	DBLP DOI BibTeX RDF	branch target address cache evaluation, sequential flow, pipeline bubbles, branch penalty, cycles per instruction, multiple instruction issue processors, branch resolution scheme, target instruction fetch, unpredictable branches, fully predicated processor architecture, fetch stage, branch target caching policies, branch target address cache, register-relative branches, performance evaluation, interrupts, interrupt, program compilers, pipeline processing, cache storage, storage allocation, instructions, program control structures, cache sizes
2	Jean-Paul Theis, Lothar Thiele	POM: a processor model for image processing. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	POM, Periodic Operation Model, optimal mapping trajectory, bus bandwidth constraints, scheduling, real-time systems, computational complexity, image processing, image processing, parallel processing, allocation, processor architecture, processor model
2	Julio Ortega, Francisco J. Pelayo, Alberto Prieto, Begoña Pino, Carlos García Puntonet	MapA: An Array Processor Architecture for Neural Networks.	IWANN	1993	DBLP DOI BibTeX RDF
2	Sukhamoy Som, Roland R. Mielke, John W. Stoughton	Prediction of Performance and Processor Requirements in Real-Time Data Flow Architectures.	IEEE Trans. Parallel Distrib. Syst.	1993	DBLP DOI BibTeX RDF	processor requirements, ATAMM, Algorithm to Architecture Mapping Model, multiprocessor operating system, reliableperformance, four-processor architecture, VHSIC 1750A Instruction Set Processor, iterative control, signal processing algorithms, nonpreemptive, dynamicmultiprocessor scheduling, processor requirement prediction, faulttolerant computing, real-timesystems, scheduling, performance, real-time systems, multiprocessing systems, operating systems (computers), periodic, data flow graph, data flow architectures
2	John G. Torborg	A parallel processor architecture for graphics arithmetic operations.	SIGGRAPH	1987	DBLP DOI BibTeX RDF
2	John L. Hennessy	VLSI Processor Architecture.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	instruction issue, processor implementation, VLSI, pipelining, microprocessors, processor architecture, Computer organization, memory mapping, instruction set design
2	Richard K. Johnsson, John D. Wick	An Overview of the Mesa Processor Architecture.	ASPLOS	1982	DBLP DOI BibTeX RDF	MESA
1	Roman Wyrzykowski, Krzysztof Rojek, Lukasz Szustak	Model-driven adaptation of double-precision matrix multiplication to the Cell processor architecture.	Parallel Computing	2012	DBLP DOI BibTeX RDF
1	Marcel D. van de Burgwal, Kenneth C. Rovers, Koen C. H. Blom, André B. J. Kokkeler, Gerard J. M. Smit	Mobile satellite reception with a virtual satellite dish based on a reconfigurable multi-processor architecture.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara	A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture.	T. HiPEAC	2011	DBLP DOI BibTeX RDF
1	Ben Abdallah Abderazek, Masashi Masuda, Arquimedes Canedo, Kenichi Kuroda	Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture.	The Journal of Supercomputing	2011	DBLP DOI BibTeX RDF
1	Martti Forsell, Ville Leppänen	A moving threads processor architecture MTPA.	The Journal of Supercomputing	2011	DBLP DOI BibTeX RDF
1	Mohsin Amin, Abbas Ramazani, Fabrice Monteiro, Camille Diou, Abbas Dandache	A Self-Checking Hardware Journal for a Fault-Tolerant Processor Architecture.	Int. J. Reconfig. Comp.	2011	DBLP DOI BibTeX RDF
1	Ling Li, Yunji Chen, Dao-Fu Liu, Cheng Qian, Weiwu Hu	An FFT Performance Model for Optimizing General-Purpose Processor Architecture.	J. Comput. Sci. Technol.	2011	DBLP DOI BibTeX RDF
1	Takefumi Miyoshi, Hideyuki Kawashima, Yuta Terada, Tsutomu Yoshinaga	A Coarse Grain Reconfigurable Processor Architecture for Stream Processing Engine.	FPL	2011	DBLP DOI BibTeX RDF	Stream Processing Engine, Reconfigurable Processor
1	Michael Kirkedal Thomsen, Holger Bock Axelsen, Robert Glück	A Reversible Processor Architecture and Its Reversible Logic Design.	RC	2011	DBLP DOI BibTeX RDF
1	Marija Kalendar, Danijela Jakimovska, Aristotel Tentov, Goce Dokoski	Novel processor architecture for modified advanced routing in NGN.	SAC	2011	DBLP DOI BibTeX RDF
1	Alberto Jimenez-Pacheco, Onkar Dabeer	A novel conflict-free memory and processor architecture for DVB-T2 LDPC decoding.	ICUMT	2011	DBLP BibTeX RDF
1	Marc de Kruijf, Karthikeyan Sankaralingam	Idempotent processor architecture.	MICRO	2011	DBLP DOI BibTeX RDF
1	Simon Hoerder, Marcin Wójcik, Stefan Tillich, Daniel Page	An Evaluation of Hash Functions on a Power Analysis Resistant Processor Architecture.	WISTP	2011	DBLP DOI BibTeX RDF
1	Minh Duc Pham, Syed Mahfuzul Aziz	FPGA-Based Image Processor Architecture for Wireless Multimedia Sensor Network.	EUC	2011	DBLP DOI BibTeX RDF
1	Walter Yuan-Hwa Li, Chin-Ling Huang, Chung-Ping Chung	Tolerating Load Miss-Latency by Extending Effective Instruction Window with Low Complexity.	ICPP	2011	DBLP DOI BibTeX RDF	Execute Ahead, Hardware Speculation, Instruction-Level Parallelism, Processor Architecture, Memory-Level Parallelism, Runahead Execution
1	Wei Huang, Karthick Rajamani, Mircea R. Stan, Kevin Skadron	Scaling with Design Constraints: Predicting the Future of Big Chips.	IEEE Micro	2011	DBLP DOI BibTeX RDF	big chips, cooling solution, power, system architecture, processor architecture, temperature, technology scaling, area, design constraints, many-core processor
1	Sergio Gálvez, David Díaz, Pilar Hernández, Francisco José Esteban, Juan Antonio Caballero, Gabriel Dorado	Next-generation bioinformatics: using many-core processor architecture to develop a web service for sequence alignment.	Bioinformatics	2010	DBLP DOI BibTeX RDF
1	Hyunjin Lee, Lei Jin, Kiyeon Lee, Socrates Demetriades, Michael Moeng, Sangyeun Cho	Two-phase trace-driven simulation (TPTS): a fast multicore processor architecture simulation approach.	Softw., Pract. Exper.	2010	DBLP DOI BibTeX RDF
1	Simon Hoerder, Marcin Wójcik, Stefan Tillich, Dan Page	An Evaluation of Hash Functions on a Power Analysis Resistant Processor Architecture.	IACR Cryptology ePrint Archive	2010	DBLP BibTeX RDF
1	Tse-Wei Chen, Chi-Sun Tang, Sung-Fang Tsai, Chen-Han Tsai, Shao-Yi Chien, Liang-Gee Chen	Tera-Scale Performance Machine Learning SoC (MLSoC) With Dual Stream Processor Architecture for Multimedia Content Analysis.	J. Solid-State Circuits	2010	DBLP DOI BibTeX RDF
1	Götz Kappen, Lothor Kurz, O. Priebe, Tobias G. Noll	Design Space Exploration for an ASIP/Co-Processor Architecture used in GNSS Receivers.	Signal Processing Systems	2010	DBLP DOI BibTeX RDF
1	Yong Dou, Jie Zhou, Guiming Wu, Jingfei Jiang, Yuanwu Lei, Shi-Ce Ni	A Unified Co-Processor Architecture for Matrix Decomposition.	J. Comput. Sci. Technol.	2010	DBLP DOI BibTeX RDF
1	Mikiko Sato, Yuji Sato, Mitaro Namiki	Proposal of a multi-core processor architecture for effective evolutionary computation.	GECCO	2010	DBLP DOI BibTeX RDF	genegic algorithms, parallel computing, evolutionary computation, multi-core processor
1	Omid Azizi, Aqeel Mahesri, Benjamin C. Lee, Sanjay J. Patel, Mark Horowitz	Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis.	ISCA	2010	DBLP DOI BibTeX RDF	co-optimization, design trade-offs, optimization, energy efficiency, design space exploration, microarchitecture
1	Kimon Karras, Thomas Wild, Andreas Herkersdorf	A folded pipeline network processor architecture for 100 Gbit/s networks.	ANCS	2010	DBLP DOI BibTeX RDF
1	Zahraa Elhassan M. Osman, Fawnizu Azmadi Hussin, Noohul Basheer Zain Ali	Optimization of Processor Architecture for Image Edge Detection Filter.	UKSim	2010	DBLP DOI BibTeX RDF
1	Minji Kim, Jinyong Lee, Younglok Kim	Fast and flexible pipelined multi-processor architecture for multimedia device.	CSNDSP	2010	DBLP BibTeX RDF
1	Yuan Xie	Processor Architecture Design Using 3D Integration Technology.	VLSI Design	2010	DBLP DOI BibTeX RDF	3D Technology, Architeture
1	Shady O. Agwa, Hany H. Ahmad, Awad I. Saleh	Hardware Pessimistic Run-Time Profiling for a Self-Reconfigurable Embedded Processor Architecture.	ReConFig	2010	DBLP DOI BibTeX RDF
1	Goran Panic, Thomas Basmer, Klaus Tittelbach-Helmrich, Lukasz Lopacinski	Low power sensor node processor architecture.	ICECS	2010	DBLP DOI BibTeX RDF
1	Alexander Heinecke, Carsten Trinitis, Josef Weidendorfer	Porting existing cache-oblivious linear algebra HPC modules to larrabee architecture.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	accelerator space-filling curve, openmp, matrix multiplication, cache-oblivious, lu decomposition, manycore
1	Dean Truong, Bevan M. Baas	Circuit modeling for practical many-core architecture design exploration.	DAC	2010	DBLP DOI BibTeX RDF	dynamic frequency and voltage scaling, control, many-core
1	Skyler Schneider, Daniel Y. Deng, Daniel Lo, Greg Malysa, G. Edward Suh	Implementing dynamic information flow tracking on microprocessors with integrated FPGA fabric (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	dynamic inspection, reconfigurable microprocessors, fpga
1	Laurence Hellyer, Richard Jones, Antony L. Hosking	The locality of concurrent write barriers.	ISMM	2010	DBLP DOI BibTeX RDF	java, garbage collection, memory management, language implementation