| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Gaetan Canivet, Paolo Maistri, Régis Leveugle, Jessy Clédière, Florent Valette, Marc Renaudin |
Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA.  |
J. Cryptology  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Paolo Maistri, Régis Leveugle |
10-Gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption Standard. |
DSD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Renaud Clavel, Laurence Pierre, Régis Leveugle |
Towards Robustness Analysis Using PVS. |
ITP |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Gaetan Canivet, Paolo Maistri, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin |
Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA. |
ASAP |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Gaetan Canivet, P. Maistn, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin |
Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA. |
European Test Symposium |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Régis Leveugle |
Early Robustness Evaluation of Digital Integrated Systems. |
FDL |
2010 |
DBLP BibTeX RDF |
|
| 1 | Régis Leveugle, Mohamed Ben Jrad |
A new methodology for accurate predictive robustness analysis of designs implemented in SRAM-based FPGAs. |
ICECS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Gaetan Canivet, Régis Leveugle, Jessy Clédière, Frédéric Valette, Marc Renaudin |
Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA. |
VTS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Régis Leveugle, A. Calvez, Paolo Maistri, Pierre Vanhauwaert |
Statistical fault injection: Quantified error and confidence. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Souheib Baarir, Cécile Braunstein, Renaud Clavel, Emmanuelle Encrenaz, Jean-Michel Ilié, Régis Leveugle, Isabelle Mounier, Laurence Pierre, Denis Poitrenaud |
Complementary Formal Approaches for Dependability Analysis. |
DFT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Paolo Maistri, Régis Leveugle |
Towards automated fault pruning with Petri Nets. |
IOLTS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Paolo Maistri, Régis Leveugle |
Double-Data-Rate Computation as a Countermeasure against Fault Analysis. |
IEEE Trans. Computers |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Paolo Maistri, Cyril Excoffon, Régis Leveugle |
Software Self-Testing of a Symmetric Cipher with Error Detection Capability. |
IOLTS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Gaetan Canivet, Jessy Clédière, Jean Baptiste Ferron, Frédéric Valette, Marc Renaudin, Régis Leveugle |
Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA. |
IOLTS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Régis Leveugle |
Early Analysis of Fault-based Attack Effects in Secure Circuits. |
IEEE Trans. Computers |
2007 |
DBLP DOI BibTeX RDF |
RTL dependability evaluation, security validation, fault models, fault injection, fault attacks |
| 1 | V. Maingot, Jean Baptiste Ferron, Régis Leveugle, Vincent Pouget, Alexandre Douin |
Configuration errors analysis in SRAM-based FPGAs: Software tool and practical results. |
Microelectronics Reliability |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Régis Leveugle, Abdelaziz Ammari, V. Maingot, E. Teyssou, Pascal Moitrel, Christophe Mourtel, Nathalie Feyt, Jean-Baptiste Rigaud, Assia Tria |
Experimental evaluation of protections against laser-induced faults and consequences on fault modeling. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Michele Portolan, Régis Leveugle |
Effective Checkpoint and Rollback Using Hardware/OS Collaboration. |
DFT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Paolo Maistri, Pierre Vanhauwaert, Régis Leveugle |
Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections. |
DFT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Paolo Maistri, Pierre Vanhauwaert, Régis Leveugle |
A Novel Double-Data-Rate AES Architecture Resistant against Fault Injection. |
FDTC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yannick Monnet, Marc Renaudin, Régis Leveugle |
Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. |
IOLTS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yannick Monnet, Marc Renaudin, Régis Leveugle |
Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
quasi-delay insensitive, hardening techniques, Asynchronous circuits, data encryption standard, fault attacks |
| 1 | Abdelaziz Ammari, Régis Leveugle, B. Nicolescu, Yvon Savaria |
Evaluation of a Software-Based Error Detection Technique by RT-Level Fault Injection. |
DELTA |
2006 |
DBLP DOI BibTeX RDF |
software hardening, fault detection, fault injection, dependability evaluation |
| 1 | Pierre Vanhauwaert, Régis Leveugle, Philippe Roche |
Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis. |
VLSI-SoC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yannick Monnet, Marc Renaudin, Régis Leveugle, Christophe Clavier, Pascal Moitrel |
Case Study of a Fault Attack on Asynchronous DES Crypto-Processors. |
FDTC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Régis Leveugle, V. Maingot |
On the Use of Information Redundancy When Designing Secure Chips. |
DDECS |
2006 |
DBLP BibTeX RDF |
|
| 1 | Pierre Vanhauwaert, Régis Leveugle, Philippe Roche |
A Flexible SoPC-based Fault Injection Environment. |
DDECS |
2006 |
DBLP BibTeX RDF |
|
| 1 | Yannick Monnet, Marc Renaudin, Régis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet |
Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor. |
IOLTS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Abdelaziz Ammari, K. Hadjiat, Régis Leveugle |
Combined Fault Classification and Error Propagation Analysis to Refine RT-Level Dependability Evaluation. |
J. Electronic Testing |
2005 |
DBLP DOI BibTeX RDF |
RT-level VHDL, 8051, fault injection, VLSI design, dependability analysis, digital circuits |
| 1 | Yannick Monnet, Marc Renaudin, Régis Leveugle |
Asynchronous circuits transient faults sensitivity evaluation. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
quasi delay insensitive, simulation, fault model, asynchronous circuits, transient fault |
| 1 | Michele Portolan, Régis Leveugle |
Towards a Secure and Reliable System. |
EUC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Michele Portolan, Régis Leveugle |
On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors. |
IOLTS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Régis Leveugle, Yervant Zorian, Luca Breveglieri, André K. Nieuwland, Klaus Rothbart, Jean-Pierre Seifert |
On-Line Testing for Secure Implementations: Design and Validation. |
IOLTS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Lorena Anghel, Régis Leveugle, Pierre Vanhauwaert |
Evaluation of SET and SEU Effects at Multiple Abstraction Levels. |
IOLTS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Régis Leveugle |
Introduction to the Special Session on Secure Implementations. |
IOLTS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Régis Leveugle |
A New Approach for Early Dependability Evaluation Based on Formal Property Checking and Controlled Mutations. |
IOLTS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yannick Monnet, Marc Renaudin, Régis Leveugle |
Hardening Techniques against Transient Faults for Asynchronous Circuits. |
IOLTS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Régis Leveugle, Abdelaziz Ammari |
Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Régis Leveugle, D. Cimonnet, Abdelaziz Ammari |
System-Level Dependability Analysis with RT-Level Fault Injection Accuracy. |
DFT |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Yannick Monnet, Marc Renaudin, Régis Leveugle |
Asynchronous Circuits Sensitivity to Fault Injection. |
IOLTS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Abdelaziz Ammari, K. Hadjiat, Régis Leveugle |
On Combining Fault Classification and Error Propagation Analysis in RT-Level Dependability Evaluation. |
IOLTS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Michele Portolan, Régis Leveugle |
Operating System Function Reuse to Achieve Low-Cost Fault Tolerance. |
IOLTS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Régis Leveugle, Glenn H. Chapman |
Special section on defect and fault tolerance in VLSI systems. |
Microelectronics Journal |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Lörinc Antoni, Régis Leveugle, Béla Fehér |
Using run-time reconfiguration for fault injection applications. |
IEEE T. Instrumentation and Measurement |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Régis Leveugle, K. Hadjiat |
Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments. |
J. Electronic Testing |
2003 |
DBLP DOI BibTeX RDF |
VHDL, fault injection, VLSI design, dependability analysis, digital circuits |
| 1 | Régis Leveugle, Lörinc Antoni, Béla Fehér |
Dependability Analysis: A New Application for Run-Time Reconfiguration. |
IPDPS |
2003 |
DBLP DOI BibTeX RDF |
hardware emulation, fault injection, dependability analysis, Digital circuits, run-time reconfiguration |
| 1 | Abdelaziz Ammari, Régis Leveugle, Matteo Sonza Reorda, Massimo Violante |
Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels. |
DFT |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Régis Leveugle |
Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Lörinc Antoni, Régis Leveugle, Béla Fehér |
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes. (PDF / PS) |
DFT |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Régis Leveugle, K. Hadjiat |
Multi-Level Fault Injection Experiments Based on VHDL Descriptions: A Case Study. |
IOLTW |
2002 |
DBLP DOI BibTeX RDF |
VHDL, fault injection, VLSI design, dependability analysis |
| 1 | Régis Leveugle |
A Low-Cost Hardware Approach to Dependability Validation of Ips. (PDF / PS) |
DFT |
2001 |
DBLP DOI BibTeX RDF |
VHDL, emulation, fault injection, dependability analysis |
| 1 | Régis Leveugle, R. Cercueil |
High Level Modifications of VHDL Descriptions for On-Line Test or Fault Tolerance. (PDF / PS) |
DFT |
2001 |
DBLP DOI BibTeX RDF |
circuit architectures, fault tolerance, VHDL, on-line testing |
| 1 | Raoul Velazco, Régis Leveugle, O. Calvo |
Upset-Like Fault Injection in VHDL Descriptions: A Method and Preliminary Results. (PDF / PS) |
DFT |
2001 |
DBLP DOI BibTeX RDF |
fuzzy logic, VHDL, fault injection |
| 1 | Lörinc Antoni, Régis Leveugle, Béla Fehér |
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes. (PDF / PS) |
DFT |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Régis Leveugle |
Fault Injection in VHDL Descriptions and Emulation. (PDF / PS) |
DFT |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Alejandro Chagoya, Régis Leveugle |
Experiments on Multimedia Support of VLSI Design teaching in the MODEM Project. |
MSE |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | X. Wendling, H. Chauvet, Lionel Revéret, R. Rochet, Régis Leveugle |
Automatic and Optimized Synthesis of Dataparts with Fault Detection or Tolerance Capabilities. (PDF / PS) |
DFT |
1997 |
DBLP DOI BibTeX RDF |
RTL synthesis, dependable VLSI circuits, fault tolerance, fault detection, CAD tools |
| 1 | X. Wendling, R. Rochet, Régis Leveugle |
Standard and ROM-based synthesis of FSMs with control flow checking capabilities. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
read-only storage, sequencing error detection, ROM architecture, finite state machines, finite state machine, integrated circuit testing, error detection, automatic testing, integrated circuit design, FSM, automatic synthesis, control flow checking |
| 1 | Régis Leveugle, Zahava Koren, Israel Koren, Gabriele Saucier, Norbert Wehn |
The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis. |
IEEE Trans. Computers |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | T. Michel, Régis Leveugle, Gabriele Saucier, R. Doucet, P. Chapier |
Taking Advantage of ASICs to Improve Dependability with Very Low Overheads. |
EDAC-ETC-EUROASIC |
1994 |
DBLP BibTeX RDF |
|
| 1 | C. Safinia, Régis Leveugle, Gabriele Saucier |
Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling. |
EDAC-ETC-EUROASIC |
1994 |
DBLP BibTeX RDF |
|
| 1 | Régis Leveugle, R. Rochet, Gabriele Saucier |
Alternative Approaches to Fault Detection in FSMs. |
DFT |
1994 |
DBLP BibTeX RDF |
|
| 1 | Régis Leveugle |
Test of single fault tolerant controllers in VLSI circuits. |
VLSI |
1993 |
DBLP BibTeX RDF |
|
| 1 | Régis Leveugle |
Optimized State Assignment of single fault Tolerant FSMs Based on SEC Codes. |
DAC |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | Régis Leveugle, R. Rochet, Gabriele Saucier, L. Martinez, C. Pitot |
A Synthesis Tool for Fault-Tolerant Finite State Machines. |
FTCS |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | R. Rochet, Régis Leveugle, Gabriele Saucier |
Analysis and Comparison of Fault Tolerant FSM Architectures Based on SEC Codes. |
DFT |
1993 |
DBLP BibTeX RDF |
|
| 1 | Régis Leveugle, X. Delord, Gabriele Saucier |
Influence of Error Correlations on the Signature Analysis Aliasing. |
ICCD |
1993 |
DBLP BibTeX RDF |
|
| 1 | Pierre Abouzeid, Régis Leveugle, Gabriele Saucier |
Logic Synthesis for Automatic Layout. |
Synthesis for Control Dominated Circuits |
1992 |
DBLP BibTeX RDF |
|
| 1 | Régis Leveugle, C. Safina |
Generation of optimized datapaths: bit-slice versus standard cells. |
Synthesis for Control Dominated Circuits |
1992 |
DBLP BibTeX RDF |
|
| 1 | L. Gerbaux, Régis Leveugle, Gabriele Saucier |
Synthesis of large controllers using ROM or PLA generators. |
Synthesis for Control Dominated Circuits |
1992 |
DBLP BibTeX RDF |
|
| 1 | C. Safina, Régis Leveugle |
Clocking scheme selection for circuits made up of a controller and a datapath. |
Synthesis for Control Dominated Circuits |
1992 |
DBLP BibTeX RDF |
|
| 1 | Margot Karam, Régis Leveugle, Gabriele Saucier |
Hierarchical Test Generation Based on Delayed Propagation. |
ITC |
1991 |
DBLP DOI BibTeX RDF |
|
| 1 | T. Michel, Régis Leveugle, Gabriele Saucier |
A New Approach to Control Flow Checking Without Program Modification. |
FTCS |
1991 |
DBLP DOI BibTeX RDF |
|
| 1 | Régis Leveugle, Gabriele Saucier |
Optimized Synthesis of Concurrently Checked Controllers. |
IEEE Trans. Computers |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | Régis Leveugle, T. Michel, Gabriele Saucier |
Design of microprocessors with built-in on-line test. |
FTCS |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | Régis Leveugle, Gabriele Saucier |
Optimized Synthesis of Dedicated Controllers with Concurrent Checking Capabilities. |
ITC |
1989 |
DBLP DOI BibTeX RDF |
|
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