Search results for "Rainer Leupers"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Rainer Leupers, Grant Martin, Roman Plyaskin, Andreas Herkersdorf, Frank Schirrmeister, Tim Kogel, Martin Vaupel	Virtual platforms: Breaking new grounds.	DATE	2012	DBLP BibTeX RDF
1	Jovana Jovic, Sergey Yakoushkin, Luis Murillo, Juan Eusse, Rainer Leupers, Gerd Ascheid	Hybrid simulation for extensible processor cores.	DATE	2012	DBLP BibTeX RDF
1	Hanno Scharwächter, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	A retargetable framework for compiler/architecture co-development.	Design Autom. for Emb. Sys.	2011	DBLP DOI BibTeX RDF
1	Stefan Kraemer, Rainer Leupers, Dietmar Petras, Thomas Philipp, Andreas Hoffmann	Checkpointing SystemC-Based Virtual Platforms.	IJERTCS	2011	DBLP DOI BibTeX RDF
1	Diandian Zhang, Han Zhang, Jerónimo Castrillón, Torsten Kempf, Bart Vanthournout, Gerd Ascheid, Rainer Leupers	Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis.	IJERTCS	2011	DBLP DOI BibTeX RDF
1	Jonghee M. Youn, Jongwon Lee, Yunheung Paek, Jongeun Lee, Hanno Scharwächter, Rainer Leupers	Fast graph-based instruction selection for multi-output instructions.	Softw., Pract. Exper.	2011	DBLP DOI BibTeX RDF
1	Jerónimo Castrillón, Weihua Sheng, Rainer Leupers	Trends in embedded software synthesis.	ICSAMOS	2011	DBLP DOI BibTeX RDF
1	Felix Engel, Rainer Leupers, Gerd Ascheid, Max Ferger, Marcel Beemster	Enhanced structural analysis for C code reconstruction from IR code.	SCOPES	2011	DBLP DOI BibTeX RDF
1	Rainer Leupers, Lieven Eeckhout, Grant Martin, Frank Schirrmeister, Nigel P. Topham, Xiaotao Chen	Virtual Manycore platforms: Moving towards 100+ processor cores.	DATE	2011	DBLP DOI BibTeX RDF
1	Torsten Kempf, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr	Analytical and Simulation-based Design Space Exploration of Software Defined Radios.	International Journal of Parallel Programming	2010	DBLP DOI BibTeX RDF
1	David Kammler, Ernst Martin Witte, Anupam Chattopadhyay, Bastian Bauwens, Gerd Ascheid, Rainer Leupers, Heinrich Meyr	Automatic Generation of Memory Interfaces for ASIPs.	IJERTCS	2010	DBLP DOI BibTeX RDF
1	Ernst Martin Witte, Filippo Borlenghi, Gerd Ascheid, Rainer Leupers, Heinrich Meyr	A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Andrea Di Biagio, Ettore Speziale, Michele Tartara, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Sotirios Xydis, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout	2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Rainer Leupers	System level MPSoC design: a bright future for compiler technology?	SCOPES	2010	DBLP DOI BibTeX RDF
1	Rainer Leupers, Jerónimo Castrillón	MPSoC programming using the MAPS compiler.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	S. Schurmans, Elias Weingärtner, Torsten Kempf, Gerd Ascheid, Klaus Wehrle, Rainer Leupers	Towards Network Centric Development of Embedded Systems.	ICC	2010	DBLP DOI BibTeX RDF
1	Jerónimo Castrillón, Ricardo Velasquez, Anastasia Stulova, Weihua Sheng, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms.	DATE	2010	DBLP BibTeX RDF
1	Rainer Leupers, Lothar Thiele, Xiaoning Nie, Bart Kienhuis, Matthias Weiss, Tsuyoshi Isshiki	Cool MPSoC programming.	DATE	2010	DBLP BibTeX RDF
1	Christoph Schumacher, Rainer Leupers, Dietmar Petras, Andreas Hoffmann	parSC: synchronous parallel systemc simulation on multi-core host architectures.	CODES+ISSS	2010	DBLP DOI BibTeX RDF
1	Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Pre- and postfabrication architecture exploration for partially reconfigurable VLIW processors.	ACM Trans. Embedded Comput. Syst.	2009	DBLP DOI BibTeX RDF	coarse-grained FPGA, VLIW, ASIP
1	Manuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	A SIMD optimization framework for retargetable compilers.	TACO	2009	DBLP DOI BibTeX RDF	SIMD, vectorization, ASIP, subword parallelism, retargetable compilers
1	Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Integrated verification approach during ADL-driven processor design.	Microelectronics Journal	2009	DBLP DOI BibTeX RDF
1	David Kammler, Diandian Zhang, Peter Schwabe, Hanno Scharwächter, Markus Langenberg, Dominik Auras, Gerd Ascheid, Rainer Leupers, Rudolf Mathar, Heinrich Meyr	Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves.	IACR Cryptology ePrint Archive	2009	DBLP BibTeX RDF
1	Ernst Martin Witte, Filippo Borlenghi, Gerd Ascheid, Rainer Leupers, Heinrich Meyr	A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding	CoRR	2009	DBLP BibTeX RDF
1	Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs).	SAMOS	2009	DBLP DOI BibTeX RDF
1	Torsten Kempf, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr	A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Rainer Leupers, Andras Vajda, Marco Bekooij, Soonhoi Ha, Rainer Dömer, Achim Nohl	Programming MPSoC platforms: Road works ahead!	DATE	2009	DBLP BibTeX RDF
1	David Kammler, Junqing Guan, Gerd Ascheid, Rainer Leupers, Heinrich Meyr	A Fast and Flexible Platform for Fault Injection and Evaluation in Verilog-Based Simulations.	SSIRI	2009	DBLP DOI BibTeX RDF
1	Jerónimo Castrillón, Diandian Zhang, Torsten Kempf, Bart Vanthournout, Rainer Leupers, Gerd Ascheid	Task management in MPSoCs: An ASIP approach.	ICCAD	2009	DBLP BibTeX RDF
1	Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	TotalProf: a fast and accurate retargetable source code profiler.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	source code profiling, architecture description language, performance estimation, instruction set simulation
1	Jianjiang Ceng, Weihua Sheng, Jerónimo Castrillón, Anastasia Stulova, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	A high-level virtual platform for early MPSoC software development.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	simulation, parallel programming, software, embedded, MPSoC, system level design, virtual platform
1	Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors.	ACM Trans. Embedded Comput. Syst.	2008	DBLP DOI BibTeX RDF	coarse-grained FPGA, VLIW, ASIP
1	Andreas Wieferink, Tim Kogel, Olaf Zerres, Rainer Leupers, Heinrich Meyr	SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends.	IJES	2008	DBLP DOI BibTeX RDF
1	Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Heinrich Meyr	Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips.	IJES	2008	DBLP DOI BibTeX RDF
1	Diandian Zhang, Anupam Chattopadhyay, David Kammler, Ernst Martin Witte, Gerd Ascheid, Rainer Leupers, Heinrich Meyr	Power-efficient Instruction Encoding Optimization for Various Architecture Classes.	JCP	2008	DBLP DOI BibTeX RDF
1	Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Chen, David Kammler, Ling Hao, Rainer Leupers, Heinrich Meyr, Gerd Ascheid	A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Lei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Multiprocessor performance estimation using hybrid simulation.	DAC	2008	DBLP DOI BibTeX RDF	HySim, address recovery, cross replay, MPSoC, performance estimation, cache simulation, hybrid simulation
1	Jianjiang Ceng, Jerónimo Castrillón, Weihua Sheng, Hanno Scharwächter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tsuyoshi Isshiki, Hiroaki Kunieda	MAPS: an integrated framework for MPSoC application parallelization.	DAC	2008	DBLP DOI BibTeX RDF	MPSoC programming, parallelization, software, embedded
1	Rainer Leupers, Gerd Ascheid, Wilfried Verachtert, Tom Ashby, Arnout Vandecappelle	System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures.	DATE	2008	DBLP DOI BibTeX RDF
1	Manuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gerrit Bette, Balpreet Singh	Retargetable Code Optimization for Predicated Execution.	DATE	2008	DBLP DOI BibTeX RDF
1	Anupam Chattopadhyay, Xiaolin Chen, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures.	DATE	2008	DBLP DOI BibTeX RDF
1	Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	ASIP architecture exploration for efficient IPSec encryption: A case study.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	computer-aided design, ADL, ASIP, IPSec
1	Oliver Schliebusch, Heinrich Meyr, Rainer Leupers	Optimized ASIP synthesis from architecture description language models.		2007	RDF
1	Anupam Chattopadhyay, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
1	Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	A fast and generic hybrid simulation approach using C virtual machine.	CASES	2007	DBLP DOI BibTeX RDF	simulation, virtual machine, debugging
1	Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations.	DATE	2007	DBLP DOI BibTeX RDF
1	Anupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Design space exploration of partially re-configurable embedded processors.	DATE	2007	DBLP DOI BibTeX RDF
1	Kingshuk Karuri, Anupam Chattopadhyay, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Increasing data-bandwidth to instruction-set extensions through register clustering.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Stefan Kraemer, Lei Gao, Jan Weinstock, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	HySim: a fast simulation framework for embedded software development.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	HySim, ISS, simulation, hybrid simulation
1	Hanno Scharwächter, Jonghee M. Youn, Rainer Leupers, Yunheung Paek, Gerd Ascheid, Heinrich Meyr	A code-generator generator for multi-output instructions.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	ISS, code-selection, compiler/architecture co-design, ASIP
1	Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers	Offset assignment using simultaneous variable coalescing.	ACM Trans. Embedded Comput. Syst.	2006	DBLP DOI BibTeX RDF	Stack offset assignment, address registers, autoincrement addressing modes, variable coalescing, DSPs, register allocation
1	Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun	Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF	C compiler retargeting, embedded processor design, architecture description language, processor model, electronic system level
1	Tim Kogel, Rainer Leupers, Heinrich Meyr	Integrated system-level modeling of network-on-chip enabled multi-processor platforms.		2006	RDF
1	Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Integrated Verification Approach during ADL-Driven Processor Design.	IEEE International Workshop on Rapid System Prototyping	2006	DBLP DOI BibTeX RDF
1	Kingshuk Karuri, Christian Huben, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Memory Access Micro-Profiling for ASIP Design.	DELTA	2006	DBLP DOI BibTeX RDF
1	Hanno Scharwächter, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	An interprocedural code optimization technique for network processors using hardware multi-threading support.	DATE	2006	DBLP DOI BibTeX RDF
1	Torsten Kempf, Kingshuk Karuri, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr	A SW performance estimation framework for early system-level-design using fine-grained instrumentation.	DATE	2006	DBLP DOI BibTeX RDF
1	Rainer Leupers, Kingshuk Karuri, Stefan Kraemer, M. Pandey	A design flow for configurable embedded processors based on optimized instruction set extension synthesis.	DATE	2006	DBLP DOI BibTeX RDF
1	Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia	Design and implementation of a modular and portable IEEE 754 compliant floating-point unit.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
1	Federico Angiolini, Jianjiang Ceng, Rainer Leupers, Federico Ferrari, Cesare Ferri, Luca Benini	An integrated open framework for heterogeneous MPSoC design space exploration.	DATE	2006	DBLP DOI BibTeX RDF
1	Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr	ASIP design and synthesis for non linear filtering in image processing.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
1	Anupam Chattopadhyay, B. Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Automatic ADL-based operand isolation for embedded processors.	DATE	2006	DBLP DOI BibTeX RDF
1	Manuel Hohenauer, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Hans van Someren	Retargetable code optimization with SIMD instructions.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	SIMD, vectorization, subword parallelism, retargetable compilers
1	Pier Stanislao Paolucci, Ahmed Amine Jerraya, Rainer Leupers, Lothar Thiele, Piero Vicini	SHAPES: : a tiled scalable software hardware architecture platform for embedded systems.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	MP-SOC, distributed network processors, hardware dependent software, network of processes, tiled parallel architectures, simulation, scheduling, embedded systems, VLIW, RISC, model based design, binding, retargetable compiler, application mapping
1	Rainer Leupers, Gerd Ascheid	Digital Signal Processors.	Handbook of Networked and Embedded Control Systems	2005	DBLP BibTeX RDF
1	Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr	Optimization Techniques for ADL-Driven RTL Processor Synthesis.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
1	Kingshuk Karuri, Mohammad Abdullah Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Fine-grained application source code profiling for ASIP design.	DAC	2005	DBLP DOI BibTeX RDF	profiling, ASIPs, codesign, customizable processors
1	Mohammad Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers	Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study.	ASAP	2005	DBLP DOI BibTeX RDF
1	Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel	A framework for automated and optimized ASIP implementation supporting multiple hardware description languages.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun	C Compiler Retargeting Based on Instruction Semantics Models.	DATE	2005	DBLP DOI BibTeX RDF
1	Torsten Kempf, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel, Bart Vanthournout	A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms.	DATE	2005	DBLP DOI BibTeX RDF
1	Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel	Retargetable generation of TLM bus interfaces for MP-SoC platforms.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	simulation, SystemC, architecture exploration, TLM, retargetability, MP-SoC
1	Gunnar Braun, Achim Nohl, Andreas Hoffmann, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr	A universal technique for fast and flexible instruction-set architecture simulation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Early ISS Integration into Network-on-Chip Designs.	SAMOS	2004	DBLP DOI BibTeX RDF
1	Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs.	SAMOS	2004	DBLP DOI BibTeX RDF
1	Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun	Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting.	SAMOS	2004	DBLP DOI BibTeX RDF
1	Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study.	SCOPES	2004	DBLP DOI BibTeX RDF
1	Gunnar Braun, Achim Nohl, Weihua Sheng, Jianjiang Ceng, Manuel Hohenauer, Hanno Scharwächter, Rainer Leupers, Heinrich Meyr	A novel approach for flexible and consistent ADL-driven ASIP design.	DAC	2004	DBLP DOI BibTeX RDF	ADL, embedded processors, ASIP
1	Markus Lorenz, Peter Marwedel, Thorsten Dräger, Gerhard Fettweis, Rainer Leupers	Compiler based exploration of DSP energy savings by SIMD operations.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl	A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform.	DATE	2004	DBLP DOI BibTeX RDF
1	Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl	RTL Processor Synthesis for Architecture Exploration and Implementation.	DATE	2004	DBLP DOI BibTeX RDF
1	Manuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren	A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models.	DATE	2004	DBLP DOI BibTeX RDF
1	Oliver Wahlen, Manuel Hohenauer, Rainer Leupers, Heinrich Meyr	Instruction Scheduler Generation for Retargetable Compilation.	IEEE Design & Test of Computers	2003	DBLP DOI BibTeX RDF
1	Oliver Wahlen, Manuel Hohenauer, Gunnar Braun, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Xiaoning Nie	Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models.	SCOPES	2003	DBLP DOI BibTeX RDF
1	Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers	Improving Offset Assignment through Simultaneous Variable Coalescing.	SCOPES	2003	DBLP DOI BibTeX RDF
1	Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr	Instruction encoding synthesis for architecture exploration using hierarchical processor models.	DAC	2003	DBLP DOI BibTeX RDF	instruction set architectures, instruction encoding
1	Rainer Leupers	Offset Assignment Showdown: Evaluation of DSP Address Code Optimization Algorithms.	CC	2003	DBLP DOI BibTeX RDF
1	Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl	Processor/Memory Co-Exploration on Multiple Abstraction Levels.	DATE	2003	DBLP DOI BibTeX RDF
1	Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens	A modular simulation framework for architectural exploration of on-chip interconnection networks.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	simulation, network-on-chip, SystemC, architecture exploration
1	Rainer Leupers	Compiler Design Issues for Embedded Processors.	IEEE Design & Test of Computers	2002	DBLP DOI BibTeX RDF
1	Andreas Hoffmann, Heinrich Meyr, Rainer Leupers	Architecture exploration for embedded processors with LISA.		2002	RDF
1	Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Andreas Hoffmann	A universal technique for fast and flexible instruction-set architecture simulation.	DAC	2002	DBLP DOI BibTeX RDF
1	Oliver Wahlen, Tilman Glökler, Achim Nohl, Andreas Hoffmann, Rainer Leupers, Heinrich Meyr	Application specific compiler/architecture codesign: a case study.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	ASIP, architecture exploration, retargetable compiler
1	Jens Wagner, Rainer Leupers	C compiler design for a network processor.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Rainer Leupers, Peter Marwedel	Retargetable compiler technology for embedded systems - tools and applications.		2001	RDF
1	Markus Lorenz, David Koffmann, Steven Bashford, Rainer Leupers, Peter Marwedel	Optimized address assignment for DSPs with SIMD memory accesses.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	Markus Lorenz, Rainer Leupers, Peter Marwedel, Thorsten Dräger, Gerhard Fettweis	Low-Energy DSP Code Generation Using a Genetic Algorithm.	ICCD	2001	DBLP BibTeX RDF
1	Jens Wagner, Rainer Leupers	C Compiler Design for an Industrial Network Processor.	LCTES/OM	2001	DBLP DOI BibTeX RDF	compilers, network processors, embedded processors
1	Rainer Leupers, Steven Bashford	Graph-based code selection techniques for embedded processors.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	code selection, irregular data paths, embedded processors, data-flow graphs, SIMD instructions
1	Rainer Leupers	Code optimization techniques for embedded processors - methods, algorithms, and tools.		2000	RDF

Publications of "Rainer Leupers" ( http://dblp.L3S.de/Authors/Rainer_Leupers )