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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 6 occurrences of 6 keywords
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Results
Found 7 publication records. Showing 7 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Rajamani Sethuram, Karim Arabi, Mohamed H. Abu-Rahma |
Leakage power profiling and leakage power reduction using DFT hardware.  |
VTS  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Sandesh Prabhakar, Rajamani Sethuram, Michael S. Hsiao |
Trace Buffer-Based Silicon Debug with Lossless Compression.  |
VLSI Design  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas |
Scan Shift Power Reduction by Gating Internal Nodes.  |
J. Low Power Electronics  |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas |
Gating internal nodes to reduce power during scan shift.  |
ACM Great Lakes Symposium on VLSI  |
2010 |
DBLP DOI BibTeX RDF |
gating internal nodes, scan shift power reduction, low power test |
| 1 | Rajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal |
Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults.  |
VTS  |
2008 |
DBLP DOI BibTeX RDF |
Diagnosis, ATPG, Fault Model, Fault Collapsing, Implication Graph |
| 1 | Rajamani Sethuram, Omar I. Khan, Hari Vijay Venkatanarayanan, Michael L. Bushnell |
A Neural Net Branch Predictor to Reduce Power.  |
VLSI Design  |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell |
Zero Cost Test Point Insertion Technique for Structured ASICs.  |
VLSI Design  |
2007 |
DBLP DOI BibTeX RDF |
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