Search results for "Rajeev Balasubramonian"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Manu Awasthi, David W. Nellans, Kshitij Sudan, Rajeev Balasubramonian, Al Davis	Managing Data Placement in Memory Systems with Multiple Memory Controllers.	International Journal of Parallel Programming	2012	DBLP DOI BibTeX RDF
1	Rajeev Balasubramonian, Vijayalakshmi Srinivasan (eds.)	2012 IEEE International Symposium on Performance Analysis of Systems & Software, New Brunswick, NJ, USA, April 1-3, 2012	ISPASS	2012	DBLP BibTeX RDF
1	Manu Awasthi, Manjunath Shevgoor, Kshitij Sudan, Bipin Rajendran, Rajeev Balasubramonian, Viji Srinivasan	Efficient scrub mechanisms for error-prone emerging memories.	HPCA	2012	DBLP DOI BibTeX RDF
1	Niladrish Chatterjee, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi	Staged Reads: Mitigating the impact of DRAM writes on DRAM reads.	HPCA	2012	DBLP DOI BibTeX RDF
1	Xiaowei Jiang, Niti Madan, Li Zhao, Mike Upton, Ravishankar Iyer, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian	CHOP: Integrating DRAM Caches for CMP Server Platforms.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Rajeev Balasubramonian, Timothy Mark Pinkston	Buses and Crossbars.	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
1	Rajeev Balasubramonian, Norman P. Jouppi, Naveen Muralimanohar	Multi-Core Cache Hierarchies		2011	DOI RDF
1	Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi	Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems.	ISCA	2011	DBLP DOI BibTeX RDF
1	Manu Awasthi, David W. Nellans, Rajeev Balasubramonian, Al Davis	Prediction Based DRAM Row-Buffer Management in the Many-Core Era.	PACT	2011	DBLP DOI BibTeX RDF
1	Gagandeep S. Sachdev, Kshitij Sudan, Mary W. Hall, Rajeev Balasubramonian	Understanding the Behavior of Pthread Applications on Non-Uniform Cache Architectures.	PACT	2011	DBLP DOI BibTeX RDF
1	Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi	Rethinking DRAM design and organization for energy-constrained multi-cores.	ISCA	2010	DBLP DOI BibTeX RDF	chipkill, dram architecture, subarrays, energy-efficiency, locality
1	David W. Nellans, Kshitij Sudan, Erik Brunvand, Rajeev Balasubramonian	Improving Server Performance on Multi-cores via Selective Off-Loading of OS Functionality.	ISCA Workshops	2010	DBLP DOI BibTeX RDF
1	David W. Nellans, Kshitij Sudan, Rajeev Balasubramonian, Erik Brunvand	Hardware prediction of OS run-length for fine-grained resource customization.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Seth H. Pugsley, Josef B. Spjut, David W. Nellans, Rajeev Balasubramonian	SWEL: hardware cache coherence protocols to map shared data onto shared caches.	PACT	2010	DBLP DOI BibTeX RDF
1	Manu Awasthi, David W. Nellans, Kshitij Sudan, Rajeev Balasubramonian, Al Davis	Handling the problems and opportunities posed by multiple on-chip memory controllers.	PACT	2010	DBLP DOI BibTeX RDF
1	Kshitij Sudan, Niladrish Chatterjee, David W. Nellans, Manu Awasthi, Rajeev Balasubramonian, Al Davis	Micro-pages: increasing DRAM efficiency with locality-aware data placement.	ASPLOS	2010	DBLP DOI BibTeX RDF	dram row-buffer management, data placement
1	Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian	Towards scalable, energy-efficient, bus-based on-chip networks.	HPCA	2010	DBLP DOI BibTeX RDF
1	Xiaowei Jiang, Niti Madan, Li Zhao, Mike Upton, Ravishankar Iyer, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian	CHOP: Adaptive filter-based DRAM caching for CMP server platforms.	HPCA	2010	DBLP DOI BibTeX RDF
1	David W. Nellans, Rajeev Balasubramonian, Erik Brunvand	OS execution on multi-cores: is out-sourcing worthwhile?	Operating Systems Review	2009	DBLP DOI BibTeX RDF
1	Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian	Non-uniform power access in large caches with low-swing wires.	HiPC	2009	DBLP DOI BibTeX RDF
1	Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha N. Udipi, Rajeev Balasubramonian, Ravishankar Iyer, Srihari Makineni, Donald Newell	Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy.	HPCA	2009	DBLP DOI BibTeX RDF
1	Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonian, John B. Carter	Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches.	HPCA	2009	DBLP DOI BibTeX RDF
1	Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi	Architecting Efficient Interconnects for Large Caches with CACTI 6.0.	IEEE Micro	2008	DBLP DOI BibTeX RDF	CACTI 6.0, on-chip interconnects, cache design
1	Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian	Scalable and reliable communication for hardware transactional memory.	PACT	2008	DBLP DOI BibTeX RDF	algorithms for transaction commit, handling message loss, on-chip network messages, token coherence, reliability, hardware transactional memory
1	Niti Madan, Rajeev Balasubramonian	Power Efficient Approaches to Redundant Multithreading.	IEEE Trans. Parallel Distrib. Syst.	2007	DBLP DOI BibTeX RDF	redundant multi-threading (RMT), dynamic frequency scaling, Reliability, power, soft errors, transient faults, heterogeneous chip multiprocessors
1	Naveen Muralimanohar, Rajeev Balasubramonian	Interconnect design considerations for large NUCA caches.	ISCA	2007	DBLP DOI BibTeX RDF	non-uniform cache architecture, network-on-chip, interconnect, memory hierarchies, cache models
1	Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi	Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0.	MICRO	2007	DBLP DOI BibTeX RDF	non-uniform cache archi- tectures (NUCA), on-chip intercon- nects, memory hierarchies, cache models
1	Niti Madan, Rajeev Balasubramonian	Leveraging 3D Technology for Improved Reliability.	MICRO	2007	DBLP DOI BibTeX RDF	redundant multi-threading, 3D die-stacking, dynamic timing errors, power-efficient microarchitecture, on-chip temperature, reliability, soft errors, parameter variation
1	Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John B. Carter	Leveraging Wire Properties at the Microarchitecture Level.	IEEE Micro	2006	DBLP DOI BibTeX RDF	interconnections, multiprocessor systems, interprocessor communications, energy-aware systems, interconnection architectures, advanced technologies
1	Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter	Interconnect-Aware Coherence Protocols for Chip Multiprocessors.	ISCA	2006	DBLP DOI BibTeX RDF
1	Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian	Power efficient resource scaling in partitioned architectures through dynamic heterogeneity.	ISPASS	2006	DBLP DOI BibTeX RDF
1	Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy	Microarchitectural Wire Management for Performance and Power in Partitioned Architectures.	HPCA	2005	DBLP DOI BibTeX RDF
1	Rajeev Balasubramonian	Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures.	ICS	2004	DBLP DOI BibTeX RDF	communication-bound processors, effective address and memory dependence prediction, processor, data prefetch, distributed caches, clustered microarchitectures
1	Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas	A Dynamically Tunable Memory Hierarchy.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	High performance microprocessors, energy and performance of on-chip caches, memory hierarchy, reconfigurable architectures
1	David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster	Dynamically Tuning Processor Resources with Adaptive Processing.	IEEE Computer	2003	DBLP DOI BibTeX RDF
1	Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi	Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors. (PDF / PS)	ISCA	2003	DBLP DOI BibTeX RDF
1	Rajeev Balasubramonian, Viji Srinivasan, Sandhya Dwarkadas, Alper Buyuktosunoglu	Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches.	PACS	2003	DBLP DOI BibTeX RDF
1	Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Greg Semeraro, Grigorios Magklis, Michael L. Scott	Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power.	IEEE PACT	2002	DBLP DOI BibTeX RDF
1	Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Michael L. Scott	Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling.	HPCA	2002	DBLP DOI BibTeX RDF	Off-Line Analysis Tool, Dynamic Reconfiguration Algorithm, Low Power, Dynamic Voltage and Frequency Scaling, Multiple Clock Domain
1	Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi	Dynamically allocating processor resources between nearby and distant ILP.	ISCA	2001	DBLP DOI BibTeX RDF
1	Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi	Reducing the complexity of the register file in dynamic superscalar processors.	MICRO	2001	DBLP DOI BibTeX RDF
1	Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas	Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures.	MICRO	2000	DBLP DOI BibTeX RDF

Publications of "Rajeev Balasubramonian" ( http://dblp.L3S.de/Authors/Rajeev_Balasubramonian )