Search results for "Rajeev Murgai"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Wanping Zhang, Wenjian Yu, Xiang Hu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng	Efficient Power Network Analysis Considering Multidomain Clock Gating.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Wanping Zhang, Yi Zhu, Wenjian Yu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Nuriyoki Ito, Chung-Kuan Cheng	Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network.	DATE	2008	DBLP DOI BibTeX RDF
1	Gustavo R. Wilke, Rajeev Murgai	Design and Analysis of "Tree+Local Meshes" Clock Architecture.	ISQED	2007	DBLP DOI BibTeX RDF
1	Vineet Wason, Rajeev Murgai, William W. Walker	An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng	Fast power network analysis with multiple clock domains.	ICCD	2007	DBLP DOI BibTeX RDF
1	Chao-Yang Yeh, Gustavo R. Wilke, Hongyu Chen, Subodh M. Reddy, Hoa-van Nguyen, Takashi Miyoshi, William W. Walker, Rajeev Murgai	Clock Distribution Architectures: A Comparative Study.	ISQED	2006	DBLP DOI BibTeX RDF
1	Subodh M. Reddy, Rajeev Murgai	Accurate Substrate Noise Analysis Based on Library Module Characterization.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Subodh M. Reddy, Gustavo R. Wilke, Rajeev Murgai	Analyzing timing uncertainty in mesh-based clock architectures.	DATE	2006	DBLP DOI BibTeX RDF
1	Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury	ADAMIN: automated, accurate macromodeling of digital aggressors for power and ground supply noise prediction.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Rajeev Murgai	Improved Layout-Driven Area-Constrained Timing Optimization by Net Buffering.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Hongyu Chen, Chao-Yang Yeh, Gustavo R. Wilke, Subodh M. Reddy, Hoa-van Nguyen, William W. Walker, Rajeev Murgai	A sliding window scheme for accurate clock mesh analysis.	ICCAD	2005	DBLP BibTeX RDF
1	Rajeev Murgai	Net Buffering in the Presence of Multiple Timing Views.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury	Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction.	DATE	2004	DBLP DOI BibTeX RDF
1	Rajeev Murgai, Subodh M. Reddy, Takashi Miyoshi, Takeshi Horie, Mehdi Baradaran Tahoori	Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis.	DATE	2004	DBLP DOI BibTeX RDF
1	Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury	Macromodeling of digital libraries for substrate noise analysis.	ISCAS	2004	DBLP BibTeX RDF
1	Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwini Verma	XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs.	ICCD	2004	DBLP DOI BibTeX RDF
1	Arlindo L. Oliveira, Rajeev Murgai	On the problem of gate assignment under different rise and fall delays.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Toshiyuki Shibuya, Rajeev Murgai, Tadashi Konno, Kazuhiro Emi, Kaoru Kawamura	PDL: A New Physical Synthesis Methodology.	ISQED	2003	DBLP DOI BibTeX RDF
1	Supratik Chakraborty, Rajeev Murgai	Layout-Driven Timing Optimization by Generalized De Morgan Transform.	VLSI Design	2002	DBLP DOI BibTeX RDF	layout-driven optimization, in-place circuit optimization, DeMorgan transformation, deep sub-micron design, Timing optimization, timing closure
1	Rajeev Murgai	Net Buffering in the Presence of Multiple Timing Views.	IWLS	2002	DBLP BibTeX RDF
1	Rajeev Murgai	Efficient global fanout optimization algorithms.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	Supratik Chakraborty, Rajeev Murgai	Complexity Of Minimum-Delay Gate Resizing.	VLSI Design	2001	DBLP DOI BibTeX RDF
1	Rajeev Murgai	Delay-Constrained Area Recovery Via Layout-Driven Buffer Optimization.	VLSI Design	2000	DBLP DOI BibTeX RDF
1	Arlindo L. Oliveira, Rajeev Murgai	An Exact Gate Assignment Algorithm for Tree Circuits Under Rise and Fall Delays.	ICCAD	2000	DBLP BibTeX RDF
1	Rajeev Murgai	Layout-Driven Area-Constrained Timing Optimization by Net Buffering.	ICCAD	2000	DBLP BibTeX RDF
1	Rajeev Murgai, Fumiyasu Hirose, Masahiro Fujita	Speeding Up Look-up-Table Driven Logic Simulation.	VLSI	1999	DBLP BibTeX RDF
1	Rajeev Murgai, Jawahar Jain, Masahiro Fujita	Efficient Scheduling Techniques for ROBDD Construction.	VLSI Design	1999	DBLP DOI BibTeX RDF
1	Rajeev Murgai, Masahiro Fujita	On Reducing Transitions Through Data Modifications.	DATE	1999	DBLP DOI BibTeX RDF
1	Rajeev Murgai	Performance optimization under rise and fall parameters.	ICCAD	1999	DBLP BibTeX RDF
1	Rajeev Murgai	On the global fanout optimization problem.	ICCAD	1999	DBLP BibTeX RDF
1	Rajeev Murgai, Masahiro Fujita, Arlindo L. Oliveira	Using Complementation and Resequencing to Minimize Transitions.	DAC	1998	DBLP DOI BibTeX RDF	reconfigurable computing, event-driven simulation
1	Rajeev Murgai, Masahiro Fujita	Some Recent Advances in Software and Hardware Logic Simulation.	VLSI Design	1997	DBLP DOI BibTeX RDF
1	Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita	Speeding up technology-independent timing optimization by network partitioning.	ICCAD	1997	DBLP DOI BibTeX RDF
1	Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose	Logic synthesis for a single large look-up table. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	single large look-up table, LUT-based field-programmable gate array architectures, simulation time minimisation, compile-code, software simulation, field programmable gate arrays, Boolean function, logic design, logic synthesis, hardware accelerator, programmable logic arrays, table lookup, logic simulation, FPGA architectures, logic functions, on-chip memory, memory constraint
1	Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Optimum Functional Decomposition Using Encoding.	DAC	1994	DBLP DOI BibTeX RDF
1	Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Sequential Synthesis for Table Look Up Programmable Gate Arrays.	DAC	1993	DBLP DOI BibTeX RDF	XILINX 3000
1	Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Cube-packing and two-level minimization.	ICCAD	1993	DBLP DOI BibTeX RDF
1	Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Some Results on the Complexity of Boolean Functions for Table Look Up Architectures.	ICCD	1993	DBLP BibTeX RDF
1	Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	An Improved Synthesis Algorithm for Multiplexor-Based PGA's.	DAC	1992	DBLP BibTeX RDF
1	Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Improved Logic Synthesis Algorithms for Table Look Up Architectures.	ICCAD	1991	DBLP BibTeX RDF
1	Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Performance Directed Synthesis for Table Look Up Programmable Gate Arrays.	ICCAD	1991	DBLP BibTeX RDF
1	Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	On Clustering for Minimum Delay/Area.	ICCAD	1991	DBLP BibTeX RDF
1	Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Logic Synthesis for Programmable Gate Arrays.	DAC	1990	DBLP DOI BibTeX RDF

Publications of "Rajeev Murgai" ( http://dblp.L3S.de/Authors/Rajeev_Murgai )