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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 11 occurrences of 8 keywords
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Results
Found 13 publication records. Showing 13 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Cecilia Metra, Rajesh Galivanche |
Guest Editors' Introduction: Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems.  |
IEEE Trans. Computers  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Suriyaprakash Natarajan, Arun Krishnamachary, Eli Chiprout, Rajesh Galivanche |
Path coverage based functional test generation for processor marginality validation.  |
ITC  |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Amir Nahir, Avi Ziv, Rajesh Galivanche, Alan J. Hu, Miron Abramovici, Albert Camilleri, Bob Bentley, Harry Foster, Valeria Bertacco, Shakti Kapoor |
Bridging pre-silicon verification and post-silicon validation.  |
DAC  |
2010 |
DBLP DOI BibTeX RDF |
post-silicon, pre-silicon, verification, validation |
| 1 | Daniele Rossi, Martin Omaña, Gianluca Berghella, Cecilia Metra, Abhijit Jas, Chandra Tirumurti, Rajesh Galivanche |
Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors.  |
Conf. Computing Frontiers  |
2010 |
DBLP DOI BibTeX RDF |
microprocessor, on-line testing, control logic |
| 1 | Gadi Singer, Rajesh Galivanche, Srinivas Patil, Mike Tripp |
The Challenges of Nanotechnology and Gigacomplexity.  |
IEEE Design & Test of Computers  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Cecilia Metra, Daniele Rossi, Martin Omaña, Abhijit Jas, Rajesh Galivanche |
Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic.  |
European Test Symposium  |
2008 |
DBLP DOI BibTeX RDF |
microprocessor, error detecting codes, on-line testing, control logic |
| 1 | Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche |
A low-cost concurrent error detection technique for processor control logic.  |
DATE  |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Rajesh Galivanche, Rohit Kapur, Antonio Rubio |
Testing in the year 2020.  |
DATE  |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Rajesh Galivanche, Bob Gottlieb |
Session Abstract.  |
VTS  |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Rajesh Galivanche |
Is the concern for soft-error overblown?  |
ITC  |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Sandip Kundu, T. M. Mak, Rajesh Galivanche |
Trends in manufacturing test methods and their implications.  |
ITC  |
2004 |
DBLP DOI BibTeX RDF |
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| 1 | Bill Grundmann, Rajesh Galivanche, Sandip Kundu |
Circuit and Platform Design Challenges in Technologies beyond 90nm.  |
DATE  |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Sandip Kundu, Sujit T. Zachariah, Sanjay Sengupta, Rajesh Galivanche |
Test Challenges in Nanometer Technologies.  |
J. Electronic Testing  |
2001 |
DBLP DOI BibTeX RDF |
circuit marginality testing, process marginality testing, defect based testing, path delay testing |
Displaying result #1 - #13 of 13 (100 per page; Change: )
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