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Found 16 publication records. Showing 16 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Ramamurthy Vishweshwara, Nagabhiru Mahita, Ramakrishnan Venkatraman |
Placement aware clock gate cloning and redistribution methodology.  |
ISQED  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Srinivas Vooka, Khushboo Agarwal, Abhijeet Shrivastava, Pranav Murthy, Ramakrishnan Venkatraman |
A Silicon Testing Strategy for Pulse-Width Failures. |
VLSI Design |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | S. M. Stalin, Amit Brahme, Ramakrishnan Venkatraman, Ajoy Mandal |
DFM: Impact analysis in a high performance design. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Sreekanth Soman, Amit Brahme, Ramakrishnan Venkatraman, Raashid Shaikh, Santhosh Thiyagaraja, Mahendrasing Patil |
Ensuring On-Die Power Supply Robustness in High-Performance Designs. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | R. Venkatraman, R. Castagnetti, Andres Teene, Benjamin Mbouombouo, S. Ramesh |
Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Parimala Viswanath, Pranav Murthy, Debajit Das, R. Venkatraman, Ajoy Mandal, Arvind Veeravalli, H. Udayakumar |
Optimization strategies to improve statistical timing. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | R. Venkatraman, Shrikrishna Pundoor, Arun Koithyar, Madhusudan Rao, Jagdish C. Rao |
Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, Vipul Kadodwala |
Early clock prototyping for design analysis and quality entitlement. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, H. Udayakumar, N. V. Arvind |
An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | R. Venkatraman, R. Castagnetti, S. Ramesh |
The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Bhaskar J. Karmakar, V. Kalyana Chakravarty, R. Venkatraman, Jagdish C. Rao |
Enabling Quality and Schedule Predictability in SoC Design using HandoffQC. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | R. Castagnetti, R. Venkatraman, B. Bartz, C. Monzel, T. Briscoe, Andres Teene, S. Ramesh |
A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva, S. Ramesh |
Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability. |
ISQED |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji |
Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
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| 1 | R. Venkatraman, S. Venkatraman |
Rule-based system application for a technical problem in inventory issue. |
AI in Engineering |
2000 |
DBLP DOI BibTeX RDF |
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| 1 | R. Venkatraman, Lalit M. Patnaik |
An evolutionary approach to timing driven FPGA placement. |
ACM Great Lakes Symposium on VLSI |
2000 |
DBLP DOI BibTeX RDF |
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