Search results for "Ramalingam Sridhar"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Geethapriya Thamilarasu, Ramalingam Sridhar	A cross-layer game for energy-efficient jamming detection in ad hoc networks.	Security and Communication Networks	2012	DBLP DOI BibTeX RDF
1	Mohammad Iftekhar Husain, Lokesh Mandvekar, Chunming Qiao, Ramalingam Sridhar	How to Bypass Verified Boot Security in Chromium OS	CoRR	2012	DBLP BibTeX RDF
1	Geethapriya Thamilarasu, Sumita Mishra, Ramalingam Sridhar	Improving Reliability of Jamming Attack Detection in Ad hoc Networks.	IJCNIS	2011	DBLP BibTeX RDF
1	Jinhui Wang, Na Gong, Ligang Hou, Xiaohong Peng, Ramalingam Sridhar, Wuchen Wu	Leakage current, active power, and delay analysis of dynamic dual Vt CMOS circuits under P-V-T fluctuations.	Microelectronics Reliability	2011	DBLP DOI BibTeX RDF
1	Mohammad Iftekhar Husain, Suyash Mahant, Ramalingam Sridhar	CD-PHY: Physical Layer Security in Wireless Networks through Constellation Diversity	CoRR	2011	DBLP BibTeX RDF
1	Na Gong, Jinhui Wang, Ramalingam Sridhar	PVT variations aware optimal sleep vector determination of dual VT domino OR circuits.	SoCC	2011	DBLP DOI BibTeX RDF
1	Na Gong, Geng Tang, Jinhui Wang, Ramalingam Sridhar	Novel adaptive keeper LBL technique for low power and high performance register files.	SoCC	2011	DBLP DOI BibTeX RDF
1	Na Gong, Geng Tang, Jinhui Wang, Ramalingam Sridhar	Low power tri-state register files design for modern out-of-order processors.	SoCC	2011	DBLP DOI BibTeX RDF
1	Ashok Narasimhan, Ramalingam Sridhar	Variability Aware Low-Power Delay Optimal Buffer Insertion for Global Interconnects.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Mohammad Iftekhar Husain, Ibrahim M. Baggili, Ramalingam Sridhar	A Simple Cost-Effective Framework for iPhone Forensic Analysis.	ICDF2C	2010	DBLP DOI BibTeX RDF
1	Thomas Büchner, Ramalingam Sridhar, Andrew Marshall, Norbert Schuhmann (eds.)	Annual IEEE International SoC Conference, SoCC 2010, September 27-29, 2010, Las Vegas, NV, USA, Proceedings	SoCC	2010	DBLP BibTeX RDF
1	Na Gong, Ramalingam Sridhar	Optimization and predication of leakage current characteristics in wide domino OR gates under PVT variation.	SoCC	2010	DBLP DOI BibTeX RDF
1	Mohammad Iftekhar Husain, Ramalingam Sridhar	D-RNA: Towards a DDoS Resistant Network Architecture using Social Network Analysis.	CAINE	2009	DBLP BibTeX RDF
1	Geethapriya Thamilarasu, Ramalingam Sridhar	Game Theoretic Modeling of Jamming Attacks in Ad hoc Networks.	ICCCN	2009	DBLP DOI BibTeX RDF
1	Mohammad Iftekhar Husain, Ramalingam Sridhar	iForensics: Forensic Analysis of Instant Messaging on Smart Phones.	ICDF2C	2009	DBLP DOI BibTeX RDF
1	Ashok Narasimhan, Ramalingam Sridhar	Variation aware low power buffered interconnect design.	SoCC	2009	DBLP DOI BibTeX RDF
1	Lushan Liu, Pradeep Nagaraj, Shambhu J. Upadhyaya, Ramalingam Sridhar	Defect Analysis and Defect Tolerant Design of Multi-port SRAMs.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Multi-port SRAMs, Defect/fault tolerant design, Defect analysis
1	Ashok Narasimhan, Ramalingam Sridhar	A low power and low area active clock deskewing technique for sub-90nm technologies.	SoCC	2008	DBLP DOI BibTeX RDF
1	Ashok Narasimhan, Ramalingam Sridhar	Impact of Variability on Clock Skew in H-tree Clock Networks.	ISQED	2007	DBLP DOI BibTeX RDF
1	Geethapriya Thamilarasu, Ramalingam Sridhar	Toward Building a Multi-level Robust Intrusion Detection Architecture for Distributed Mobile Networks.	ICDCS Workshops	2007	DBLP DOI BibTeX RDF
1	Vidya Bharrgavi Balasubramanyn, Geethapriya Thamilarasu, Ramalingam Sridhar	Security Solution For Data Integrity InWireless BioSensor Networks.	ICDCS Workshops	2007	DBLP DOI BibTeX RDF
1	Manjari Agarwal, Praveen Elakkumanan, Ramalingam Sridhar	Intra-die process parameter variation and leakage analysis of cache at the microarchitectural level.	SoCC	2007	DBLP DOI BibTeX RDF
1	Varun V. Ramaswamy, Manjari Agarwal, Ramalingam Sridhar	Robust 3GHz CMOS low noise amplifier adapted for RFID receivers.	SoCC	2007	DBLP DOI BibTeX RDF
1	Praveen Elakkumanan, Kishan Prasad, Ramalingam Sridhar	Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic.	ISQED	2006	DBLP DOI BibTeX RDF
1	Praveen Elakkumanan, Jente B. Kuang, Kevin J. Nowka, Ramalingam Sridhar, Rouwaida Kanj, Sani R. Nassif	SRAM Local Bit Line Access Failure Analyses.	ISQED	2006	DBLP DOI BibTeX RDF
1	Srikanth Sundaram, Praveen Elakkumanan, Ramalingam Sridhar	High Speed Robust Current Sense Amplifier for Nanoscale Memories: - A Winner Take All Approach.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Ashok Narasimhan, Bhooma Srinivasaraghavan, Ramalingam Sridhar	A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling Scheme for Global Interconnects.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Lushan Liu, Ramalingam Sridhar, Shambhu J. Upadhyaya	A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells.	DFT	2006	DBLP DOI BibTeX RDF
1	Prachee Sharma, Asheq Khan, Ashok Narasimhan, Ramalingam Sridhar, Satish K. Tripathi	Energy Conservation in Sensor Networks through Selective Node Activation.	WOWMOM	2006	DBLP DOI BibTeX RDF
1	Praveen Elakkumanan, Kishan Prasad, Ramalingam Sridhar	Low Power SER Tolerant Design to Mitigate Single Event Transients in Nanoscale Circuits.	J. Low Power Electronics	2005	DBLP DOI BibTeX RDF
1	V. Natarajan, Aruna Balasubramanian, Sumita Mishra, Ramalingam Sridhar	Security for Energy Constrained RFID System.	AutoID	2005	DBLP DOI BibTeX RDF
1	Geethapriya Thamilarasu, Aruna Balasubramanian, Sumita Mishra, Ramalingam Sridhar	A cross-layer based intrusion detection approach for wireless ad hoc networks.	MASS	2005	DBLP DOI BibTeX RDF
1	Charan Thondapu, Praveen Elakkumanan, Ramalingam Sridhar	RG-SRAM: A Low Gate Leakage Memory Design.	ISVLSI	2005	DBLP DOI BibTeX RDF
1	Ashok Narasimhan, Shantanu Divekar, Praveen Elakkumanan, Ramalingam Sridhar	A Low-Power Current-Mode Clock Distribution Scheme for Multi-GHz NoC-Based SoCs.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Ashok Narasimhan, Manish Kasotiya, Ramalingam Sridhar	A Low-Swing Differential Signaling Scheme for On-Chip Global Interconnects.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Ramalingam Sridhar	System-on-Chip (SoC): Clocking and Synchronization Issues.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Ranjani Sridharan, Ramalingam Sridhar, Sumita Mishra	A robust header compression technique for wireless Ad hoc networks.	Mobile Computing and Communications Review	2003	DBLP DOI BibTeX RDF
1	Rajesh S. Parthasarathy, Ramalingam Sridhar	Double Pass Transistor Logic for High Performance Wave Pipeline Circuits.	VLSI Design	1998	DBLP DOI BibTeX RDF
1	Wen-jann Yang, Ramalingam Sridhar, Paul W. Palumbo	Multi-attribute Lexicon Generation by Hyper-linked Embedded Access Structure.	IDEAS	1997	DBLP BibTeX RDF
1	Seokjin Kim, Ramalingam Sridhar	Self-Timed Mesochronous Interconnection for High-Speed VLSI Systems. (PDF / PS)	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
1	Wen-jann Yang, Ramalingam Sridhar, Victor Demjanenko	Parallel Intersecting Compressed Bit Vectors in a High Speed Query Server for Processing Postal Addresses.	HPCA	1996	DBLP DOI BibTeX RDF	List intersection hardware, Parallel architecture, Compression, Inverted file
1	Sreejit Chakravarty, Ramalingam Sridhar, Shambhu J. Upadhyaya, Yervant Zorian, Gil Philips, Bozena Kaminska, Bernard Courtois	Conference Reports.	IEEE Design & Test of Computers	1995	DBLP BibTeX RDF
1	Seokjin Kim, Ramalingam Sridhar	A local clocking approach for self-timed datapath designs.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	self-timed datapath designs, local clock control circuit, synchronous datapaths, asynchronous environment, locally-clocked multiplier, asynchronous system implementation, timing, logic design, logic design, digital arithmetic, asynchronous circuits, multiplying circuits
1	Ram K. Krishnamurthy, Ramalingam Sridhar	A CMOS wave-pipelined image processor for real-time morphology . (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	CMOS wave-pipelined image processor, real-time morphology, high-speed morphological image processor, wave-pipelined transmission gate logic, two-stage morphological skeleton transform filter, regular pipelined architectures, real-time systems, computational complexity, image processing, latency, pipeline processing, CMOS integrated circuits, hardware complexity
1	Xuguang Zhang, Ramalingam Sridhar	Synchronization of Wave-Pipelined Circuits.	ICCD	1994	DBLP BibTeX RDF
1	Martin S. Gilbert, Ramalingam Sridhar	AMEC - Asynchronous microprogram execution controller.	Microprocessing and Microprogramming	1992	DBLP DOI BibTeX RDF
1	Paul W. Palumbo, Sargur N. Srihari, Jung Soh, Ramalingam Sridhar, Victor Demjanenko	Postal Address Block Location in Real Time.	IEEE Computer	1992	DBLP DOI BibTeX RDF

Publications of "Ramalingam Sridhar" ( http://dblp.L3S.de/Authors/Ramalingam_Sridhar )