Search results for "Ramon Canal"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Enric Herrero, José González, Ramon Canal	Distributed Cooperative Caching: An Energy Efficient Memory Scheme for Chip Multiprocessors.	IEEE Trans. Parallel Distrib. Syst.	2012	DBLP DOI BibTeX RDF
1	Nivard Aymerich, Shrikanth Ganapathy, Antonio Rubio, Ramon Canal, Antonio González	Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells.	Integration	2012	DBLP DOI BibTeX RDF
1	Ramon Canal, Antonio Rubio, A. Asenov, A. Brown, Miguel Miranda, Paul Zuber, Antonio González, Xavier Vera	TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies.	Procedia CS	2011	DBLP DOI BibTeX RDF
1	Nivard Aymerich, Shrikanth Ganapathy, Antonio Rubio, Ramon Canal, Antonio González	Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Nivard Aymerich, A. Asenov, A. Brown, Ramon Canal, B. Cheng, Joan Figueras, Antonio González, Enric Herrero, S. Markov, Miguel Miranda, P. Pouyan, Tanausu Ramirez, Antonio Rubio, I. Vatajelu, Xavier Vera, X. Wang, Paul Zuber	New reliability mechanisms in memory design for sub-22nm technologies.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio	Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors.	ICCD	2011	DBLP DOI BibTeX RDF
1	Enric Herrero, José González, Ramon Canal	Power-Efficient Spilling Techniques for Chip Multiprocessors.	Euro-Par	2010	DBLP DOI BibTeX RDF
1	Enric Herrero, José González, Ramon Canal	Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors.	ISCA	2010	DBLP DOI BibTeX RDF	elastic cooperative caching, tiled microarchitectures, chip multiprocessors, memory hierarchy
1	Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio	MODEST: a model for energy estimation under spatio-temporal variability.	ISLPED	2010	DBLP DOI BibTeX RDF	dsm scaling, spatio-temporal variability, cache design
1	Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio	Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability.	DATE	2010	DBLP BibTeX RDF
1	Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro López, José Duato	An hybrid eDRAM/SRAM macrocell to implement first-level data caches.	MICRO	2009	DBLP DOI BibTeX RDF	retention time, static and dynamic memory cells, leakage current
1	Matteo Monchiero, Ramon Canal, Antonio González	Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs.	ICPP	2009	DBLP DOI BibTeX RDF
1	Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks	Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability.	IEEE Micro	2008	DBLP DOI BibTeX RDF	caches, process variation, variability, dynamic memory
1	Matteo Monchiero, Ramon Canal, Antonio González	Power/Performance/Thermal Design-Space Exploration for Multicore Architectures.	IEEE Trans. Parallel Distrib. Syst.	2008	DBLP DOI BibTeX RDF	simulation of, Modeling, evaluation, Measurement, Parallel Architectures, Shared memory, Energy-aware systems, multiple-processor systems
1	Enric Herrero, José González, Ramon Canal	Distributed cooperative caching.	PACT	2008	DBLP DOI BibTeX RDF	distributed cooperative caching, energy efficiency, chip multiprocessors, memory hierarchy
1	Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks	Process Variation Tolerant 3T1D-Based Cache Architectures.	MICRO	2007	DBLP DOI BibTeX RDF
1	Matteo Monchiero, Ramon Canal, Antonio González	Design space exploration for multicore architectures: a power/performance/thermal view.	ICS	2006	DBLP DOI BibTeX RDF
1	Ramon Canal, Antonio González, James E. Smith	Value Compression for Efficient Computation.	Euro-Par	2005	DBLP DOI BibTeX RDF
1	Ramon Canal, Antonio González, James E. Smith	Software-Controlled Operand-Gating.	CGO	2004	DBLP DOI BibTeX RDF
1	Jaume Abella, Ramon Canal, Antonio González	Power- and Complexity-Aware Issue Queue Designs.	IEEE Micro	2003	DBLP DOI BibTeX RDF
1	Ramon Canal, Joan-Manuel Parcerisa, Antonio González	Dynamic Code Partitioning for Clustered Architectures.	International Journal of Parallel Programming	2001	DBLP DOI BibTeX RDF
1	Ramon Canal, Antonio González	Reducing the complexity of the issue logic.	ICS	2001	DBLP DOI BibTeX RDF	complexity-effective design, instruction issue logic, wide-issue superscalar, out-of-order issue
1	Ramon Canal, Antonio González, James E. Smith	Very low power pipelines using significance compression.	MICRO	2000	DBLP DOI BibTeX RDF
1	Ramon Canal, Antonio González	A low-complexity issue logic.	ICS	2000	DBLP DOI BibTeX RDF	in-order issue, instruction issue logic, wide-issue superscalar, out-of-order issue
1	Ramon Canal, Joan-Manuel Parcerisa, Antonio González	Dynamic Cluster Assignment Mechanisms.	HPCA	2000	DBLP DOI BibTeX RDF	dynamic code partitioning, steering logic, Clustered microarchitectures, dynamically scheduled processors
1	Ramon Canal, Joan-Manuel Parcerisa, Antonio González	A Cost-Effective Clustered Architecture.	IEEE PACT	1999	DBLP DOI BibTeX RDF	code partitioning, dynamic steering, inter-cluster communication, cluster, microarchitecture, clustered architecture, workload balance

Publications of "Ramon Canal" ( http://dblp.L3S.de/Authors/Ramon_Canal )