Search results for "Ran Ginosar"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Dmitri Vainbrand, Ran Ginosar	Scalable network-on-chip architecture for configurable neural networks.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Ran Ginosar	Metastability and Synchronizers: A Tutorial.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF	FIFO synchronizer, mesochronous, multisynchronous, synchronizer, asynchronous, design and test, metastability
1	Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny	An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Rostislav (Reuven) Dobkin, Michael Moyal, Avinoam Kolodny, Ran Ginosar	Asynchronous Current Mode Serial Communication.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny	Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696].	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny	Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Dmitri Vainbrand, Ran Ginosar	Network-on-Chip Architectures for Neural Networks.	NOCS	2010	DBLP DOI BibTeX RDF	Neural Network, Network-on-Chip
1	Amit Berman, Ran Ginosar, Idit Keidar	Order is power: Selective Packet Interleaving for energy efficient Networks-on-Chip.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman	Timing-driven variation-aware nonuniform clock mesh synthesis.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	clock mesh synthesis, non-tree clock networks, vlsi cad, power, process variations, physical design, clock skew, clock distribution
1	Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny	The Devolution of Synchronizers.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Rostislav (Reuven) Dobkin, Ran Ginosar	Two-phase synchronization with sub-cycle latency.	Integration	2009	DBLP DOI BibTeX RDF
1	Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny	QNoC asynchronous router.	Integration	2009	DBLP DOI BibTeX RDF
1	Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman	Power efficient tree-based crosslinks for skew reduction.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	crosslink, non-tree clock distribution network, power, mesh, skew, clock tree
1	Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser	Multiple clock and voltage domains for chip multi processors.	MICRO	2009	DBLP DOI BibTeX RDF	clock domains, voltage domain, power management, DVFS, chip multi processor
1	Asaf Baron, Ran Ginosar, Isaac Keslassy	The Capacity Allocation Paradox.	INFOCOM	2009	DBLP DOI BibTeX RDF
1	A. Elyada, Ran Ginosar, Uri C. Weiser	Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Rostislav (Reuven) Dobkin, Ran Ginosar	Fast Universal Synchronizers.	PATMOS	2008	DBLP DOI BibTeX RDF	MCD, Synchronization, SoC
1	Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny	Timing optimization in logic with interconnect.	SLIP	2008	DBLP DOI BibTeX RDF	interconnect, logic circuits, timing optimization, repeaters, logical effort
1	Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar	Parallel vs. serial on-chip communication.	SLIP	2008	DBLP DOI BibTeX RDF	dual-rail, long-range interconnect serial link, parallel link, asynchronous circuits
1	Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny	Network Delays and Link Capacities in Application-Specific Wormhole NoCs.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Rami Rom, Jacob Erel, Michael Glikson, Randy A. Lieberman, Kobi Rosenblum, Ofer Binah, Ran Ginosar, David L. Hayes	Adaptive Cardiac Resynchronization Therapy Device Based on Spiking Neurons Architecture and Reinforcement Learning Scheme.	IEEE Transactions on Neural Networks	2007	DBLP DOI BibTeX RDF
1	Rostislav (Reuven) Dobkin, Ran Ginosar, Israel Cidon	QNoC Asynchronous Router with Dynamic Virtual Channel Allocation.	NOCS	2007	DBLP DOI BibTeX RDF
1	Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny	Access Regulation to Hot-Modules in Wormhole NoCs.	NOCS	2007	DBLP DOI BibTeX RDF	SoC, resource management, Network on-Chip, hotspot, wormhole
1	Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny	The Power of Priority: NoC Based Distributed Cache Coherency.	NOCS	2007	DBLP DOI BibTeX RDF
1	Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny	High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny	Routing table minimization for irregular mesh NoCs.	DATE	2007	DBLP DOI BibTeX RDF
1	Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou	High Rate Data Synchronization in GALS SoCs.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Ilya Obridko, Ran Ginosar	Minimal Energy Asynchronous Dynamic Adders.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Uri Frank, Tsachy Kapschitz, Ran Ginosar	A predictive synchronizer for periodic clock domains.	Formal Methods in System Design	2006	DBLP DOI BibTeX RDF	Predictive Synchronizer, Multiple Clock Domains (MCD), Formal Verification, Systems on Chip (SoC), Clock Synchronization, Metastability
1	Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny	Fast Asynchronous Shift Register for Bit-Serial Communication.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny	Efficient link capacity and QoS design for network-on-chip.	DATE	2006	DBLP DOI BibTeX RDF
1	Rostislav (Reuven) Dobkin, Michael Peleg, Ran Ginosar	Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Rostislav (Reuven) Dobkin, Victoria Vishnyakov, Eyal Friedman, Ran Ginosar	An Asynchronous Router for Multiple Service Levels Networks on Chip.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Tsachy Kapschitz, Ran Ginosar	Formal Verification of Synchronizers.	CHARME	2005	DBLP DOI BibTeX RDF
1	Ilya Obridko, Ran Ginosar	Low energy asynchronous architectures.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny	Low-leakage repeaters for NoC interconnects.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny	QNoC: QoS architecture and design process for network on chip.	Journal of Systems Architecture	2004	DBLP DOI BibTeX RDF
1	Arkadiy Morgenshtein, Michael Moreinis, Ran Ginosar	Asynchronous gate-diffusion-input (GDI) circuits.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny	Cost considerations in network on chip.	Integration	2004	DBLP DOI BibTeX RDF
1	Uri Frank, Ran Ginosar	A Predictive Synchronizer for Periodic Clock Domains.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou	Data Synchronization Issues in GALS SoCs.	ASYNC	2004	DBLP DOI BibTeX RDF
1	Alex Branover, Rakefet Kol, Ran Ginosar	Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones.	DATE	2004	DBLP DOI BibTeX RDF
1	Y. Elboim, Avinoam Kolodny, Ran Ginosar	A clock-tuning circuit for system-on-chip.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Ken S. Stevens, Ran Ginosar, Shai Rotem	Relative timing [asynchronous design].	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Yaron Semiat, Ran Ginosar	Timing Measurements of Synchronization Circuits.	ASYNC	2003	DBLP DOI BibTeX RDF
1	Ran Ginosar	Fourteen Ways to Fool Your Synchronizer.	ASYNC	2003	DBLP DOI BibTeX RDF
1	Ken S. Stevens, Shai Rotem, Ran Ginosar	Relative Timing.	ASYNC	1999	DBLP DOI BibTeX RDF
1	Shai Rotem, Ken S. Stevens, Charles Dike, Marly Roncken, Boris Agapiev, Ran Ginosar, Rakefet Kol, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun	RAPPID: An Asynchronous Instruction Length Decoder.	ASYNC	1999	DBLP DOI BibTeX RDF
1	Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken	CAD Directions for High Performance Asynchronous Circuits.	DAC	1999	DBLP DOI BibTeX RDF
1	Uzi Zangi, Ran Ginosar	A low power video processor.	ISLPED	1998	DBLP DOI BibTeX RDF
1	Wei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Ken S. Stevens, Kenneth Y. Yun	Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits.	ASYNC	1998	DBLP DOI BibTeX RDF
1	Rakefet Kol, Ran Ginosar	Kin: A High Performance Asynchronous Processor Architecture.	International Conference on Supercomputing	1998	DBLP DOI BibTeX RDF	asynchronous architecture, avid execution, dynamic instance tag, multi-execution, pruning
1	Rakefet Kol, Ran Ginosar	A Double-Latched Asynchronous Pipeline.	ICCD	1997	DBLP BibTeX RDF
1	Ilana David, Ran Ginosar, Michael Yoeli	Self-timed is self-checking.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	finite state machines, asynchronous systems, combinational logic, self-checkings, self-timed
1	Alan Rotman, Ran Ginosar	Control unit synthesis from a high-level language.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
1	Ilana David, Ran Ginosar, Michael Yoeli	Self-Timed Architecture of a Reduced Instruction Set Computer.	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
1	Ilana David, Ran Ginosar, Michael Yoeli	An Efficient Implementation of Boolean Functions as Self-Timed Circuits.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	logic module, temporal logic, temporal logic, Boolean functions, Boolean functions, logic design, correctness, logic circuits, automatic synthesis, formal proof, self-timed circuits, functional constraints
1	Ilana David, Ran Ginosar, Michael Yoeli	Implementing Sequential Machines as Self-Timed Circuits.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	temporal behaviour constraints, master-slave register, state table, finite state machine, logic design, finite automata, sequential machines, combinational logic, combinatorial mathematics, self-timed circuits, automatic compiler
1	Arie Harsat, Ran Ginosar	CARMEL-4: The Unify-Spawn Machine for FCP.	ICLP	1991	DBLP BibTeX RDF
1	Arie Harsat, Ran Ginosar	CARMEL-2: A second generation VLSI architecture for Flat Concurrent Prolog.	New Generation Comput.	1990	DBLP DOI BibTeX RDF
1	Arie Harsat, Ran Ginosar	An Extended RISC Methodology and its Application to FCP.	ICLP	1990	DBLP BibTeX RDF
1	Ran Ginosar, David Egozi	Topological comparison of perfect shuffle and hypercube.	International Journal of Parallel Programming	1989	DBLP DOI BibTeX RDF
1	Arie Harsat, Ran Ginosar	CARMEL-2: A Second Generation VLSI Architecture for Flat Concurrent Prolog.	FGCS	1988	DBLP BibTeX RDF
1	Ran Ginosar, Dwight D. Hill	Design and Implementation of Switching Systems for Parallel Processors.	ICPP	1985	DBLP BibTeX RDF
1	Bruce W. Arden, Ran Ginosar	Performance evaluation of the MP/C.	AFIPS National Computer Conference	1983	DBLP DOI BibTeX RDF
1	Bruce W. Arden, Ran Ginosar	MP/C: A Multiprocessor/Computer Architecture.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF
1	Bruce W. Arden, Ran Ginosar	MP/C: A Multiprocessor/Computer Architecture.	ISCA	1981	DBLP BibTeX RDF
1	Bruce W. Arden, Ran Ginosar	A Single-Relation Module for a Data Base Machine.	ISCA	1981	DBLP BibTeX RDF

Publications of "Ran Ginosar" ( http://dblp.L3S.de/Authors/Ran_Ginosar )