| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Annie Avakian, Natwar Agrawal, Ranga Vemuri |
Reconfigurable Multicore Architecture for Dynamic Processor Reallocation.  |
ARC  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hao Xu, Ranga Vemuri, Wen-Ben Jone |
Dynamic Characteristics of Power Gating During Mode Transition. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hao Xu, Wen-Ben Jone, Ranga Vemuri |
Aggressive Runtime Leakage Control Through Adaptive Light-Weight Vth Hopping With Temperature and Process Variation. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Amayika Panda, Annie Avakian, Ranga Vemuri |
Configurable workload generators for multicore architectures. |
SoCC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hao Xu, Wen-Ben Jone, Ranga Vemuri |
Tuning Vth Hopping for Aggressive Runtime Leakage Control. |
J. Low Power Electronics |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Annie Avakian, Jon Nafziger, Amayika Panda, Ranga Vemuri |
A reconfigurable architecture for multicore systems. |
IPDPS Workshops |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hao Xu, Wen-Ben Jone, Ranga Vemuri |
Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jon Nafziger, Annie Avakian, Ranga Vemuri |
A prediction-based, data Migration Algorithm for hybrid Architecture NoC systems. |
SoCC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hao Xu, Ranga Vemuri, Wen-Ben Jone |
Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hao Xu, Wen-Ben Jone, Ranga Vemuri |
Stretching the limit of microarchitectural level leakage control with Adaptive Light-Weight Vth Hopping. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Balasubramanian Sethuraman, Ranga Vemuri |
A methodology for application-specific NoC architecture generation in a dynamic task structure environment. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
dynamic task graphs, networks-on-chip, bandwidth |
| 1 | Angan Das, Ranga Vemuri |
Fuzzy Logic Based Guidance to Graph Grammar Framework for Automated Analog Circuit Design. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Shubhankar Basu, Balaji Kommineni, Ranga Vemuri |
Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Almitra Pradhan, Ranga Vemuri |
Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Angan Das, Ranga Vemuri |
A graph grammar based approach to automated multi-objective analog circuit design. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Hao Xu, Ranga Vemuri, Wen-Ben Jone |
Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Hao Xu, Ranga Vemuri, Wen-Ben Jone |
Temporal and spatial idleness exploitation for optimal-grained leakage control. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Romana Fernandes, Ranga Vemuri |
Accurate estimation of vector dependent leakage power in the presence of process variations. |
ICCD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Shubhankar Basu, Balaji Kommineni, Ranga Vemuri |
Variation Aware Spline Center and Range Modeling for Analog Circuit Performance. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
Center and Range, Process Variation, Analog, Spline |
| 1 | Hao Xu, Ranga Vemuri, Wen-Ben Jone |
Dynamic virtual ground voltage estimation for power gating. |
ISLPED |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Angan Das, Ranga Vemuri |
A Self-learning Optimization Technique for Topology Design of Computer Networks. |
EvoWorkshops |
2008 |
DBLP DOI BibTeX RDF |
Self-learning search, Constrained optimization, Topology design, MPLS networks |
| 1 | Almitra Pradhan, Ranga Vemuri |
A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
layout-aware, matrix-models, sizing |
| 1 | Angan Das, Ranga Vemuri |
Topology synthesis of analog circuits based on adaptively generated building blocks. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
genetic algorithm, automated design, topology generation |
| 1 | Almitra Pradhan, Ranga Vemuri |
On the Use of Hash Tables for Efficient Analog Circuit Synthesis. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Shubhankar Basu, Balaji Kommineni, Ranga Vemuri |
Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Srividhya Rammohan, Vijay Sundaresan, Ranga Vemuri |
Reduced Complementary Dynamic and Differential Logic: A CMOS Logic Style for DPA-Resistant Secure IC Design. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Almitra Pradhan, Ranga Vemuri |
Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Angan Das, Ranga Vemuri |
ATLAS: An adaptively formed hierarchical cell library based analog synthesis framework. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hao Xu, Wen-Ben Jone, Ranga Vemuri |
Accurate energy breakeven time estimation for run-time power gating. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hao Xu, Ranga Vemuri, Wen-Ben Jone |
Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Raoul F. Badaoui, Ranga Vemuri |
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis |
CoRR |
2007 |
DBLP BibTeX RDF |
|
| 1 | Jawad Khan, Ranga Vemuri |
An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms |
CoRR |
2007 |
DBLP BibTeX RDF |
|
| 1 | Shubhankar Basu, Priyanka Thakore, Ranga Vemuri |
Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Angan Das, Ranga Vemuri |
An Automated Passive Analog Circuit Synthesis Framework using Genetic Algorithms. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Shubhankar Basu, Ranga Vemuri |
Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Balasubramanian Sethuraman, Ranga Vemuri |
Multicasting based topology generation and core mapping for a power efficient networks-on-chip. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
packet reduction, power-efficient core mapping, multicast, networks-on-chip, mesh topology |
| 1 | Almitra Pradhan, Ranga Vemuri |
Regression based circuit matrix models for accurate performance estimation of analog circuits. |
VLSI-SoC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Vijay Sundaresan, Srividhya Rammohan, Ranga Vemuri |
Power invariant secure IC design methodology using reduced complementary dynamic and differential logic. |
VLSI-SoC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Balaji Kommineni, Shubhankar Basu, Ranga Vemuri |
A spline based regression technique on interval valued noisy data. |
ICMLA |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Huiying Yang, Ranga Vemuri |
Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit Synthesis. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Balasubramanian Sethuraman, Ranga Vemuri |
A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Angan Das, Ranga Vemuri |
GAPSYS: A GA-based Tool for Automated Passive Analog Circuit Synthesis. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Balasubramanian Sethuraman, Ranga Vemuri |
Power variations of multi-port routers in an application-specific NoC design : A case study. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Nagu R. Dhanwada, Alex Doboli, Adrián Núñez-Aldana, Ranga Vemuri |
Hierarchical constraint transformation based on genetic optimization for analog system synthesis. |
Integration |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Balasubramanian Sethuraman, Ranga Vemuri |
Multi2 Router: A Novel Multi Local Port Router Architecture with Broadcast Facility for FPGA-Based Networks-on-Chip. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Vijay Sundaresan, Ranga Vemuri |
A Novel Approach to Performance-Oriented Datapath Allocation and Floorplanning. |
ISVLSI |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Renqiu Huang, Ranga Vemuri |
Transformation synthesis for data intensive applications to FPGAs. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ritochit Chakraborty, Mukesh Ranjan, Ranga Vemuri |
Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits Using an Efficient Symbolic Newton-Iteration Algorithm for Pole Extraction. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Mengmeng Ding, Ranga Vemuri |
Efficient Analog Performance Macromodeling via Sequential Design Space Decomposition. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Amitava Bhaduri, Ranga Vemuri |
Parasitic Aware Routing Methodology Based on Higher Order RLCK Moment Metrics. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Xin Jia, Ranga Vemuri |
CAD Tools for a Globally Asynchronous Locally Synchronous FPGA Architecture. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Balasubramanian Sethuraman, Ranga Vemuri |
optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Huiying Yang, Ranga Vemuri |
Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in analog circuit synthesis. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Mukesh Ranjan, Ranga Vemuri |
Exact hierarchical symbolic analysis of large analog networks using a general interconnection template. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Xin Jia, Ranga Vemuri |
Studying a GALS FPGA architecture using a parameterized automatic design flow. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Manish Handa, Ranga Vemuri |
Hardware assisted two dimensional ultra fast online placement. |
IJES |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jawad Khan, Ranga Vemuri |
Energy Management in Battery-Powered Sensor Networks with Reconfigurable Computing Nodes. |
FPL |
2005 |
DBLP BibTeX RDF |
|
| 1 | Renqiu Huang, Ranga Vemuri |
PAHLS: Towards Run-Time Synthesis for FPGAs. |
FPL |
2005 |
DBLP BibTeX RDF |
|
| 1 | Xin Jia, Ranga Vemuri |
A Novel Asynchronous FPGA Architecture Design and Its Performance Evaluation. |
FPL |
2005 |
DBLP BibTeX RDF |
|
| 1 | Huiying Yang, Anuradha Agarwal, Ranga Vemuri |
Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient Diagrams. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Renqiu Huang, Ranga Vemuri |
Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Balasubramanian Sethuraman, Prasun Bhattacharya, Jawad Khan, Ranga Vemuri |
LiPaR: A light-weight parallel router for FPGA-based networks-on-chip. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
SoCRouter, FPGA, networks-on-chip |
| 1 | Anuradha Agarwal, Glenn Wolfe, Ranga Vemuri |
Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
performance modeling, circuit sizing, analog synthesis |
| 1 | Amitava Bhaduri, Ranga Vemuri |
Moment-driven coupling-aware routing methodology. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
coupling-aware, routing, moments |
| 1 | Jawad Khan, Ranga Vemuri |
Battery-Efficient Task Execution on Reconfigurable Computing Platforms with Multiple Processing Units. |
IPDPS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Mengmeng Ding, Ranga Vemuri |
A combined feasibility and performance macromodel for analog circuits. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
feasibility models, performance macromodeling, active learning |
| 1 | Huiying Yang, Mukesh Ranjan, Wim Verhaegen, Mengmeng Ding, Ranga Vemuri, Georges G. E. Gielen |
Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Mengmeng Ding, Glenn Wolfe, Ranga Vemuri |
An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Xin Jia, Ranga Vemuri |
Using GALS architecture to reduce the impact of long wire delay on FPGA performance. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Xin Jia, Ranga Vemuri |
The GAPLA: A Globally Asynchronous Locally Synchronous FPGA Architecture. |
FCCM |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Madhubanti Mukherjee, Ranga Vemuri |
On Physical-Aware Synthesis of Vertically Integrated 3D Systems. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Mengmeng Ding, Ranga Vemuri |
An Active Learning Scheme Using Support Vector Machines for Analog Circuit Feasibility Classification. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Renqiu Huang, Ranga Vemuri |
On-Line Synthesis for Partially Reconfigurable FPGAs. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Raoul F. Badaoui, Ranga Vemuri |
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Mengmeng Ding, Ranga Vemuri |
A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jawad Khan, Ranga Vemuri |
An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Amitava Bhaduri, Ranga Vemuri |
Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Raoul F. Badaoui, Ranga Vemuri |
Analog VLSI circuit-level synthesis using multi-placement structures. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Anuradha Agarwal, Ranga Vemuri |
Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Anuradha Agarwal, Ranga Vemuri |
Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Alex Doboli, Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri |
A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications. |
ACM Trans. Design Autom. Electr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
genetic algorithms, branch-and-bound, performance estimation, VHDL-AMS, Analog synthesis |
| 1 | Xin Jia, Jayanthi Rajagopalan, Ranga Vemuri |
A Dynamically Reconfigurable Asynchronous FPGA Architecture. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Jawad Khan, Ranga Vemuri |
An Efficient Battery-Aware Task Scheduling Methodology for Portable RC Platforms. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Renqiu Huang, Manish Handa, Ranga Vemuri |
Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAs. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Manish Handa, Ranga Vemuri |
An Integrated Online Scheduling and Placement Methodology. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Jawad Khan, Balasubramanian Sethuraman, Ranga Vemuri |
A Power-Performance Trade-off Methodology for Portable Reconfigurable Platforms. |
ERSA |
2004 |
DBLP BibTeX RDF |
|
| 1 | Jawad Khan, Jayanthi Rajagopalan, Renqiu Huang, Ranga Vemuri |
A Portable Face Recognition System Using Reconfigurable Hardware. |
ERSA |
2004 |
DBLP BibTeX RDF |
|
| 1 | Manish Handa, Ranga Vemuri |
Area Fragmentation in Reconfigurable Operating Systems. |
ERSA |
2004 |
DBLP BibTeX RDF |
|
| 1 | Raoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri |
A high level language for pre-layout extraction in parasite-aware analog circuit synthesis. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
MSL, pre-layout extraction, parasitics, analog VLSI |
| 1 | Renqiu Huang, Ranga Vemuri |
Forward-Looking Macro Generation and Relational Placement During High Level Synthesis to FPGAs. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
critical net, performance, placement, Behavioral synthesis, macro |
| 1 | Manish Handa, Ranga Vemuri |
Hardware Assisted Two Dimensional Ultra Fast Placement. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri |
Fast and accurate parasitic capacitance models for layout-aware. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
layout aware, parasitic estimation, analog synthesis |
| 1 | Manish Handa, Ranga Vemuri |
An efficient algorithm for finding empty space for online FPGA placement. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
online placement, partially reconfigurable FPGAs, reconfigurable computing |
| 1 | Xin Jia, Ranga Vemuri |
A Design Methodology for Self-Timed Event Logic Pipelines. |
ESA/VLSI |
2004 |
DBLP BibTeX RDF |
|
| 1 | Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri |
Accurate Estimation of Parasitic Capacitances in Analog Circuits. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen |
Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Manish Handa, Ranga Vemuri |
A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic FPGA Placement. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Renqiu Huang, Ranga Vemuri |
Analysis and evaluation of a hybrid interconnect structure for FPGAs. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Ranga Vemuri, Glenn Wolfe |
Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Madhubanti Mukherjee, Ranga Vemuri |
Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems. |
ICCD |
2004 |
DBLP DOI BibTeX RDF |
|
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