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Publications of "Reiley Jeyapaul" ( http://dblp.L3S.de/Authors/Reiley_Jeyapaul )

  Author page on DBLP  Author page in RDF  Community of Reiley Jeyapaul in ASPL-2

Publication years (Num. hits)
2008 (1) 2009 (1) 2010 (3) 2011 (3)
Publication types (Num. hits)
article(1) inproceedings(7)
Venues (Conferences, Journals, ...)
GrowBag graphs for keyword ? (Num. hits/coverage)

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The graphs summarize 13 occurrences of 11 keywords

Results
Found 8 publication records. Showing 8 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Reiley Jeyapaul, Fei Hong, Abhishek Rhisheekesan, Aviral Shrivastava, Kyoungwoo Lee UnSync: A Soft Error Resilient Redundant Multicore Architecture. Search on Bibsonomy ICPP The full citation details ... 2011 DBLP  DOI  BibTeX  RDF core-level redundancy, redundant architecture, hardware detection, low power, soft error, error resilient, multi-core architecture
1Aviral Shrivastava, Jared Pager, Reiley Jeyapaul, Mahdi Hamzeh, Sarma B. K. Vrudhula Enabling Multithreading on CGRAs. Search on Bibsonomy ICPP The full citation details ... 2011 DBLP  DOI  BibTeX  RDF CGRA, processor accelerator, dynamic threading, runtime scheduling, page-based mapping, CGRA mapping technique, low power, multithreading, compiler optimization, scheduling technique
1Reiley Jeyapaul, Aviral Shrivastava Smart cache cleaning: energy efficient vulnerability reduction in embedded processors. Search on Bibsonomy CASES The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Reiley Jeyapaul, Aviral Shrivastava Code Transformations for TLB Power Reduction. Search on Bibsonomy International Journal of Parallel Programming The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Reiley Jeyapaul, Aviral Shrivastava B2P2: bounds based procedure placement for instruction TLB power reduction in embedded systems. Search on Bibsonomy SCOPES The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Aviral Shrivastava, Jongeun Lee, Reiley Jeyapaul Cache vulnerability equations for protecting data in embedded processor caches from soft errors. Search on Bibsonomy LCTES The full citation details ... 2010 DBLP  DOI  BibTeX  RDF cache vulnerability, static analysis, embedded processors, soft errors, code transformation, compiler technique
1Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivastava Code Transformations for TLB Power Reduction. Search on Bibsonomy VLSI Design The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Reiley Jeyapaul, Yunheung Paek SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures. Search on Bibsonomy ASP-DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
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