| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Arash Zargaran-Yazd, Shahriar Mirabbasi, Res Saleh |
A 10 Gb/s low-power serdes receiver based on a hybrid speculative/SAR digitization technique.  |
ISCAS  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | J. G. Mueller, Resve A. Saleh |
Autonomous, Multilevel Ring Tuning Scheme for Post-Silicon Active Clock Deskewing Over Intra-Die Variations. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab K. Ward |
Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Dipanjan Sengupta, Resve A. Saleh |
Application-Driven Voltage-Island Partitioning for Low-Power System-on-Chip Design. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiongfei Meng, Resve A. Saleh |
Active decap design considerations for optimal supply noise reduction. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sohaib Majzoub, Resve Saleh, Rabab K. Ward |
PVT variation impact on voltage island formation in MPSoC design. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiongfei Meng, Resve Saleh, Steven J. E. Wilton |
Charge-borrowing decap: A novel circuit for removal of local supply noise violations. |
CICC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sohaib Majzoub, Resve Saleh, Steven J. E. Wilton, Rabab Kreidieh Ward |
Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT. |
SoCC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiongfei Meng, Resve A. Saleh, Karim Arabi |
Layout of Decoupling Capacitors in IP Blocks for 90-nm CMOS. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Zahra Sadat Ebadi, Resve A. Saleh |
A Fully-Integrated 2.4 GHz Mismatch-Controllable RF Front-end Test Platform in 0.18µm CMOS. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
Mismatch-Controllable, RF front-end, IQ mismatch, Direct conversion receiver, IEEE 802.11g |
| 1 | Jeff Mueller, Resve A. Saleh |
A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Uthman Alsaiari, Resve A. Saleh |
Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
Partitioning, Redundancy, Yield, Flip-Flop |
| 1 | Dipanjan Sengupta, Resve A. Saleh |
Application-driven floorplan-aware voltage island design. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
dynamic programming, energy, floorplan, voltage island |
| 1 | Dipanjan Sengupta, Resve A. Saleh |
Supply voltage selection in Voltage Island based SoC design. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter Hallschmid, Resve Saleh |
Fast Design Space Exploration Using Local Regression Modeling With Application to ASIPs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Zahra Sadat Ebadi, Resve Saleh |
Adaptive Compensation of RF Front-End Nonidealities in Direct Conversion Receivers. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeff Mueller, Resve Saleh |
Single Edge Clock (SEC) Distribution for Improved Latency, Skew, and Jitter Performance. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Tatsuya Koyagi, Masahiro Fukui, Resve Saleh |
Delay macromodeling and estimation for RTL. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Cristian Grecu, André Ivanov, Resve A. Saleh, Partha Pratim Pande |
Testing Network-on-Chip Communication Fabrics. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Karim Arabi, Resve A. Saleh, Xiongfei Meng |
Power Supply Noise in SoCs: Metrics, Management, and Measurement. |
IEEE Design & Test of Computers |
2007 |
DBLP DOI BibTeX RDF |
metrics, DFT, power supply noise, deep-submicron, production test, power integrity |
| 1 | Dipanjan Sengupta, Resve Saleh |
Generalized Power-Delay Metrics in Deep Submicron CMOS Designs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Zahra Sadat Ebadi, Alireza Nasiri Avanaki, Resve Saleh, André Ivanov |
Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip. |
Integration |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Uthman Alsaiari, Resve Saleh |
Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Resve Saleh, Pallab K. Chatterjee, Ivan Pesic, Robbert Dobkins, Mike Smayling, Joseph Sawicki |
DFM-EDA's Salvation or its Excuse for Being out of Touch with Engineering? |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter Hallschmid, Resve Saleh |
Automatic Cache Tuning for Energy-Efficiency using Local Regression Modeling. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiongfei Meng, Karim Arabi, Resve Saleh |
A Novel Active Decoupling Capacitor Design in 90nm CMOS. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Kedia, Resve Saleh |
Power Reduction of On-Chip Serial Links. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Cristian Grecu, Lorena Anghel, Partha Pratim Pande, André Ivanov, Resve Saleh |
Essential Fault-Tolerance Metrics for NoC Infrastructures. |
IOLTS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh |
BIST for Network-on-Chip Interconnect Infrastructures. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
interconnect infrastructure, unicast test, multicast test, built-in self-test, network-on-chip |
| 1 | Cristian Grecu, André Ivanov, Res Saleh, Partha Pratim Pande |
NoC Interconnect Yield Improvement Using Crosspoint Redundancy. |
DFT |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Cristian Grecu, André Ivanov, Res Saleh, Egor S. Sogomonyan, Partha Pratim Pande |
On-line Fault Detection and Location for NoC Interconnects. |
IOLTS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiongfei Meng, Resve A. Saleh, Karim Arabi |
Novel Decoupling Capacitor Designs for sub- 90nm CMOS Technology. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Reza Molavi, Shahriar Mirabbasi, Resve A. Saleh |
A high-speed low-energy dynamic PLA using an input-isolation scheme. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Victor Aken Ova, Resve Saleh |
A "Soft++" eFPGA Physical Design Approach with Case Studies in 180nm and 90nm. |
ISVLSI |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter Hallschmid, Resve Saleh |
Fast Configuration of an Energy-Efficient Branch Predictor. |
ISVLSI |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Uthman Alsaiari, Resve Saleh |
Testable and self-repairable structured logic design. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh |
Timing analysis of network on chip architectures for MP-SoC platforms. |
Microelectronics Journal |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Res Saleh |
Effect of traffic localization on energy dissipation in NoC-based interconnect. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Cristian Grecu, Partha Pratim Pande, Baosheng Wang, André Ivanov, Res Saleh |
Methodologies and Algorithms for Testing Switch-Based NoC Interconnects. |
DFT |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh |
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
system-on-chip, Network-on-chip, interconnect architecture, MP-SoC, infrastructure IP |
| 1 | Resve A. Saleh |
An approach that will NoC your SoCs off! |
IEEE Design & Test of Computers |
2005 |
DBLP DOI BibTeX RDF |
networks on chips, SoC design, Moore's law, interconnect delay, IP blocks |
| 1 | Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, Giovanni De Micheli |
Design, Synthesis, and Test of Networks on Chips. |
IEEE Design & Test of Computers |
2005 |
DBLP DOI BibTeX RDF |
Reliability, VLSI, Automatic synthesis, VLSI Systems, Testing and Fault-Tolerance |
| 1 | Dipanjan Sengupta, Resve A. Saleh |
Power-Delay Metrics Revisited for 90nm CMOS Technology. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh |
A Scalable Communication-Centric SoC Interconnect Architecture. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
switch-based interconnect, butterfly fat-tree, global wire delay, System on chip, interconnect architecture, timing closure |
| 1 | Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh |
Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
BFT, scalability, pipelining, bus, MP-SoC |
| 1 | Partha Pratim Pande, Cristian Grecu, André Ivanov, Res Saleh |
Design of a switch for network on chip applications. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | S. Shang, Shahriar Mirabbasi, Resve A. Saleh |
A technique for DC-offset removal and carrier phase error compensation in integrated wireless receivers. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Mama Hamour, Resve A. Saleh, Shahriar Mirabbasi, André Ivanov |
Analog IP design flow for SoC applications. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Resve A. Saleh, G. Lim, T. Kadowaki, K. Uchiyama |
Trends in Low Power Digital System-on-Chip Designs (invited). (PDF / PS) |
ISQED |
2002 |
DBLP DOI BibTeX RDF |
Low-Power CMOS, Design, SoC, Digital |
| 1 | Mohsen Nahvi, André Ivanov, Resve A. Saleh |
Dedicated Autonomous Scan-Based Testing (DAST) for Embedded Cores. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Resve A. Saleh, Syed Zakir Hussain, Steffen Rochel, David Overhauser |
Clock skew verification in the presence of IR-drop in the powerdistribution network. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Resve A. Saleh, David Overhauser, Sandy Taylor |
Full-chip verification of UDSM designs. |
ICCAD |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Resve A. Saleh, Brian A. A. Antao, Jaidip Singh |
Multilevel and mixed-domain simulation of analog circuits and systems. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | J. G. Mueller, Brian A. A. Antao, Resve A. Saleh |
A multifrequency technique for frequency response computation with application to switched-capacitor circuits with nonlinearities. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Yen-Cheng Wen, Kyle Gallivan, Resve A. Saleh |
Improving Parallel Circuit Simulation Using High-Level Waveforms. |
ISCAS |
1995 |
DBLP BibTeX RDF |
|
| 1 | Gih-Guang Hung, Yen-Cheng Wen, Kyle Gallivan, Resve A. Saleh |
Improving the performance of parallel relaxation-based circuit simulators. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | Eugene Z. Xia, Resve A. Saleh |
Parallel waveform-Newton algorithms for circuit simulation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1992 |
DBLP DOI BibTeX RDF |
|
| 1 | Yun-Cheng Ju, Resve A. Saleh |
Incremental Circuit Simulation Using Waveform Relaxation. |
DAC |
1992 |
DBLP BibTeX RDF |
|
| 1 | Ken Kubiak, Steven Parkes, W. Kent Fuchs, Resve A. Saleh |
Exact Evaluation of Diagnostic Test Resolution. |
DAC |
1992 |
DBLP BibTeX RDF |
|
| 1 | Yun-Cheng Ju, Vasant B. Rao, Resve A. Saleh |
Consistency checking and optimization of macromodels. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1991 |
DBLP DOI BibTeX RDF |
|
| 1 | Yun-Cheng Ju, Resve A. Saleh |
Incremental Techniques for the Identification of Statically Sensitizable Critical Paths. |
DAC |
1991 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaidip Singh, Resve A. Saleh |
iMACSIM: A Program for Multi-Level Analog Circuit Simulation. |
ICCAD |
1991 |
DBLP BibTeX RDF |
|
| 1 | Yun-Cheng Ju, Resve A. Saleh |
Identification of Viable Paths Using Binary Decision Diagrams. |
ICCD |
1991 |
DBLP BibTeX RDF |
|
| 1 | Yen-Cheng Wen, Kyle Gallivan, Resve A. Saleh |
Parallel Event-Driven Waveform Relaxation. |
ICCD |
1991 |
DBLP BibTeX RDF |
|
| 1 | Resve A. Saleh, Jacob K. White |
Accelerating relaxation algorithms for circuit simulation using waveform-Newton and step-size refinement. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | Gih-Guang Hung, Yen-Cheng Wen, Kyle Gallivan, Resve A. Saleh |
Parallel Circuit Simulation Using Hierarchical Relaxation. |
DAC |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | Yun-Cheng Ju, Fred L. Yang, Resve A. Saleh |
Mixed-Mode Incremental Simulation and Concurrent Fault Simulation. |
ICCAD |
1990 |
DBLP BibTeX RDF |
|
| 1 | Resve A. Saleh, A. Richard Newton |
The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1989 |
DBLP DOI BibTeX RDF |
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")