Search results for "Rob A. Rutenbar"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Wangyang Zhang, Xin Li, Frank Liu, Emrah Acar, Rob A. Rutenbar, Ronald D. Blanton	Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Wangyang Zhang, Karthik Balakrishnan, Xin Li, Duane S. Boning, Rob A. Rutenbar	Toward efficient spatial variation decomposition via sparse regression.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Amith Singhee, Rob A. Rutenbar	Why Quasi-Monte Carlo is Better Than Monte Carlo or Latin Hypercube Sampling for Statistical Circuit Analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Jiajing Wang, Amith Singhee, Rob A. Rutenbar, Benton H. Calhoun	Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Rob A. Rutenbar	Analog layout synthesis: what's missing?	ISPD	2010	DBLP DOI BibTeX RDF	synthesis, layout, analog
1	Wangyang Zhang, Xin Li, Rob A. Rutenbar	Bayesian virtual probe: minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference.	DAC	2010	DBLP DOI BibTeX RDF	variation characterization, process variation, integrated circuit
1	Wangyang Zhang, Xin Li, Emrah Acar, Frank Liu, Rob A. Rutenbar	Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Amith Singhee, Rob A. Rutenbar	Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Amith Singhee, Rob A. Rutenbar	Novel Algorithms for Fast Statistical Analysis of Scaled Circuits		2009	DBLP DOI BibTeX RDF
1	Patrick Groeneveld, Rob A. Rutenbar, Jed W. Pitera, Erik C. Carlson, Jinsong Chen	Oil fields, hedge funds, and drugs.	DAC	2009	DBLP DOI BibTeX RDF	financial market analysis, oil field discovery, Monte Carlo methods, drug discovery
1	Edward C. Lin, Rob A. Rutenbar	A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer.	FPGA	2009	DBLP DOI BibTeX RDF	in silico vox, fpga, speech recognition, dsp
1	Kai Yu, Rob A. Rutenbar	Profiling large-vocabulary continuous speech recognition on embedded devices: a hardware resource sensitivity analysis.	INTERSPEECH	2009	DBLP BibTeX RDF
1	Xin Li, Rob A. Rutenbar, R. D. (Shawn) Blanton	Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits.	ICCAD	2009	DBLP BibTeX RDF
1	Amith Singhee, Claire Fang Fang, James D. Ma, Rob A. Rutenbar	Probabilistic Interval-Valued Computation: Toward a Practical Surrogate for Statistics Inside CAD Tools.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Andreas Kuehlmann, Anjan Bose, David E. Corman, Rob A. Rutenbar, Robert M. Manning, Anna Newman	Verifying really complex systems: on earth and beyond.	DAC	2008	DBLP DOI BibTeX RDF	Mars Exploration Rover, bald lemurs, rendering software, space vehicles, verification, computer animation, power grids, avionics
1	Amith Singhee, Jiajing Wang, Benton H. Calhoun, Rob A. Rutenbar	Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Amith Singhee, Sonia Singhal, Rob A. Rutenbar	Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing.	DATE	2008	DBLP DOI BibTeX RDF
1	Patrick J. Bourke, Rob A. Rutenbar	A low-power hardware search architecture for speech recognition.	INTERSPEECH	2008	DBLP BibTeX RDF
1	Amith Singhee, Sonia Singhal, Rob A. Rutenbar	Practical, fast Monte Carlo statistical static timing analysis: why and how.	ICCAD	2008	DBLP DOI BibTeX RDF
1	James D. Ma, Rob A. Rutenbar	Interval-Valued Reduced-Order Statistical Interconnect Modeling.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee	Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters	CoRR	2007	DBLP BibTeX RDF
1	Amith Singhee, Rob A. Rutenbar	From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis.	ISQED	2007	DBLP DOI BibTeX RDF
1	Zhong Xiu, Rob A. Rutenbar	Mixed-size placement with fixed macrocells using grid-warping.	ISPD	2007	DBLP DOI BibTeX RDF	mixed-size placement, algorithms, placement
1	Amith Singhee, Rob A. Rutenbar	Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting.	DAC	2007	DBLP DOI BibTeX RDF
1	Rob A. Rutenbar	Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-Chains.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Edward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen	A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA.	FPGA	2007	DBLP DOI BibTeX RDF	in silico vox, FPGA, speech recognition, DSP
1	Amith Singhee, Rob A. Rutenbar	Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application.	DATE	2007	DBLP DOI BibTeX RDF
1	Kai Yu, Rob A. Rutenbar	Generating small, accurate acoustic models with a modified Bayesian information criterion.	INTERSPEECH	2007	DBLP BibTeX RDF
1	Goran Frehse, Bruce H. Krogh, Rob A. Rutenbar, Oded Maler	Time Domain Verification of Oscillator Circuit Properties.	Electr. Notes Theor. Comput. Sci.	2006	DBLP DOI BibTeX RDF
1	James D. Ma, Rob A. Rutenbar	Fast Interval-Valued Statistical Modeling of Interconnect and Effective Capacitance.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Amith Singhee, Claire Fang Fang, James D. Ma, Rob A. Rutenbar	Probabilistic interval-valued computation: toward a practical surrogate for statistics inside CAD tools.	DAC	2006	DBLP DOI BibTeX RDF	algorithms, DFM, intervals
1	Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar	Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration.	DAC	2006	DBLP DOI BibTeX RDF	pareto surfaces, performance space, optimization, yield
1	Goran Frehse, Bruce H. Krogh, Rob A. Rutenbar	Verifying analog oscillator circuits using forward/backward abstraction refinement.	DATE	2006	DBLP DOI BibTeX RDF
1	Edward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen	Moving speech recognition from software to silicon: the in silico vox project.	INTERSPEECH	2006	DBLP BibTeX RDF
1	Saurabh K. Tiwary, Rob A. Rutenbar	Faster, parametric trajectory-based macromodels via localized linear reductions.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Rob A. Rutenbar	Design automation for analog: the next generation of tool challenges.	ICCAD	2006	DBLP DOI BibTeX RDF	computer-aided design, synthesis, analog, integrated circuits, mixed-signal
1	James D. Z. Ma, Rob A. Rutenbar	Fast interval-valued statistical interconnect modeling and reduction.	ISPD	2005	DBLP DOI BibTeX RDF	interval-valued statistical interconnect analysis, manufacturing variation, affine arithmetic
1	Zhong Xiu, David A. Papa, Philip Chong, Christoph Albrecht, Andreas Kuehlmann, Rob A. Rutenbar, Igor L. Markov	Early research experience with OpenAccess gear: an open source development environment for physical design.	ISPD	2005	DBLP DOI BibTeX RDF	database, timing, open source, placement, physical design, EDA
1	Saurabh K. Tiwary, Rob A. Rutenbar	Scalable trajectory methods for on-demand analog macromodel extraction.	DAC	2005	DBLP DOI BibTeX RDF	trajectory method, analog, SPICE, circuit, macromodel
1	Zhong Xiu, Rob A. Rutenbar	Timing-driven placement by grid-warping.	DAC	2005	DBLP DOI BibTeX RDF	algorithms, placement
1	Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee	Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters.	DATE	2005	DBLP DOI BibTeX RDF
1	James D. Ma, Claire Fang Fang, Rob A. Rutenbar, Xiaolin Xie, Duane S. Boning	Interval-valued statistical modeling of oxide chemical-mechanical polishing.	ICCAD	2005	DBLP BibTeX RDF
1	Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar	A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
1	Zhong Xiu, James D. Z. Ma, Suzanne M. Fowler, Rob A. Rutenbar	Large-scale placement by grid-warping.	DAC	2004	DBLP DOI BibTeX RDF	algorithms, placement
1	Rob A. Rutenbar, Anthony R. Bonaccio, Teresa H. Y. Meng, Ernesto Perea, Robert Pitts, Charles Sodini, Jim Wieser	Will Moore's Law rule in the land of analog?	DAC	2004	DBLP DOI BibTeX RDF
1	Gang Zhang, E. Aykut Dengi, Ronald A. Rohrer, Rob A. Rutenbar, L. Richard Carley	A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits.	DAC	2004	DBLP DOI BibTeX RDF	modeling, synthesis, layout, sizing, parasitic, radio frequency
1	Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu	Static statistical timing analysis for latch-based pipeline designs.	ICCAD	2004	DBLP DOI BibTeX RDF
1	James D. Ma, Rob A. Rutenbar	Interval-valued reduced order statistical interconnect modeling.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Smriti Gupta, Bruce H. Krogh, Rob A. Rutenbar	Towards formal verification of analog designs.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Hui Xu, Rob A. Rutenbar, Karem A. Sakallah	sub-SAT: a formulation for relaxed Boolean satisfiability with applications in routing.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Rob A. Rutenbar, David L. Harame, Kurt Johnson, Paul Kempf, Teresa H. Y. Meng, Reza Rofougaran, James Spoto	Mixed signals on mixed-signal: the right next technology.	DAC	2003	DBLP DOI BibTeX RDF
1	Claire Fang Fang, Rob A. Rutenbar, Markus Püschel, Tsuhan Chen	Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling.	DAC	2003	DBLP DOI BibTeX RDF	Static error analysis, custom floating-point, embedded hardware, probabilistic error bound, affine arithmetic
1	Claire Fang Fang, Rob A. Rutenbar, Tsuhan Chen	Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Claire Fang Fang, Tsuhan Chen, Rob A. Rutenbar	Lightweight Floating-Point Arithmetic: Case Study of Inverse Discrete Cosine Transform.	EURASIP J. Adv. Sig. Proc.	2002	DBLP DOI BibTeX RDF
1	Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar	A new FPGA detailed routing approach via search-based Booleansatisfiability.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar	Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search.	FPL	2002	DBLP DOI BibTeX RDF
1	Hui Xu, Rob A. Rutenbar, Karem A. Sakallah	sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing.	ISPD	2002	DBLP DOI BibTeX RDF
1	Hongzhou Liu, Amith Singhee, Rob A. Rutenbar, L. Richard Carley	Remembrance of circuits past: macromodeling by data mining in large analog design spaces.	DAC	2002	DBLP DOI BibTeX RDF
1	Rony Kay, Rob A. Rutenbar	Wire packing - a strong formulation of crosstalk-aware chip-leveltrack/layer assignment with an efficient integer programming solution.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Rob A. Rutenbar, L. Richard Carley, Roberto Zafalon, Nicola Dragone	Low-power technology mapping for mixed-swing logic.	ISLPED	2001	DBLP DOI BibTeX RDF
1	Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar	A comparative study of two Boolean formulations of FPGA detailed routing constraints.	ISPD	2001	DBLP DOI BibTeX RDF
1	Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen	Panel: (When) Will FPGAs Kill ASICs?	DAC	2001	DBLP DOI BibTeX RDF
1	Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar	A boolean satisfiability-based incremental rerouting approach with application to FPGAs.	DATE	2001	DBLP DOI BibTeX RDF
1	Rob A. Rutenbar	Synthesis for Industrial-Scale Analog Intellectual Property. (PDF / PS)	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
1	Rob A. Rutenbar, Olivier Coudert, Patrick Groeneveld, Jürgen Koehl, Scott Peterson, Vivek Raghavan, Naresh Soni	Automatic Hierarchical Design: Fantasy or Reality? (Panel).	ICCAD	2001	DBLP BibTeX RDF
1	Michael Krasnicki, Rodney Phelps, James R. Hellums, Mark McClung, Rob A. Rutenbar, L. Richard Carley	ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits.	ICCAD	2001	DBLP BibTeX RDF
1	Prakash Gopalakrishnan, Rob A. Rutenbar	Direct Transistor-Level Layout for Digital Blocks.	ICCAD	2001	DBLP BibTeX RDF
1	Domine Leenaerts, Rob A. Rutenbar, Georges G. E. Gielen	Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design.	ICCAD	2001	DBLP BibTeX RDF
1	Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums	Anaconda: simulation-based synthesis of analog circuits viastochastic pattern search.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
1	Tamal Mukherjee, L. Richard Carley, Rob A. Rutenbar	Efficient handling of operating range and manufacturing linevariations in analog cell synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
1	J. Y. F. Tong, David Nagle, Rob A. Rutenbar	Reducing power by optimizing the necessary precision/range of floating-point arithmetic.	IEEE Trans. VLSI Syst.	2000	DBLP DOI BibTeX RDF
1	Rob A. Rutenbar, John M. Cohn	Layout tools for analog ICs and mixed-signal SoCs: a survey.	ISPD	2000	DBLP DOI BibTeX RDF
1	Rony Kay, Rob A. Rutenbar	Wire packing: a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution.	ISPD	2000	DBLP DOI BibTeX RDF
1	Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums	A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC.	DAC	2000	DBLP DOI BibTeX RDF
1	Rob A. Rutenbar, Cheming Hu, Mark Horowitz, Stephen Y. Chow	Life at the end of CMOS scaling (and beyond) (panel session) (abstract only).	DAC	2000	DBLP DOI BibTeX RDF
1	John M. Cohn, Rob A. Rutenbar, Steve Young, Chris Malachowsky, Luis Aldaz	Case studies: Chip design on the bleeding edge (panel session abstract).	DAC	2000	DBLP DOI BibTeX RDF
1	Stephan Ohr, Rob A. Rutenbar, Henry Chang, Georges G. E. Gielen, Rudolf Koch, Roy McGuffin, K. C. Murphy	Survival strategies for mixed-signal systems-on-chip (panel session).	DAC	2000	DBLP DOI BibTeX RDF
1	Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley	Device-level early floorplanning algorithms for RF circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Pascal C. H. Meier, Rob A. Rutenbar, L. Richard Carley	Inverse polarity techniques for high-speed/low-power multipliers.	ISLPED	1999	DBLP DOI BibTeX RDF	inverse polarity, low power, multiplier
1	Michael Krasnicki, Rodney Phelps, Rob A. Rutenbar, L. Richard Carley	MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells.	DAC	1999	DBLP DOI BibTeX RDF
1	Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar	Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT.	FPGA	1999	DBLP DOI BibTeX RDF	conflict-directed search, Boolean satisfiability, FPGA routing
1	Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar	Satisfiability-Based Detailed FPGA Routing.	VLSI Design	1999	DBLP DOI BibTeX RDF
1	Sudip Nag, Rob A. Rutenbar	Performance-driven simultaneous placement and routing for FPGA's.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
1	R. Glenn Wood, Rob A. Rutenbar	FPGA routing and routability estimation via Boolean satisfiability.	IEEE Trans. VLSI Syst.	1998	DBLP DOI BibTeX RDF
1	Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley	Device-level early floorplanning algorithms for RF circuits.	ISPD	1998	DBLP DOI BibTeX RDF
1	R. Glenn Wood, Rob A. Rutenbar	FPGA Routing and Routability Estimation via Boolean Satisfiability.	FPGA	1997	DBLP DOI BibTeX RDF
1	Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar	A hierarchical decomposition methodology for multistage clock circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	performance driven router, routing, process variations, manufacturability, clock
1	Emil S. Ochotta, Rob A. Rutenbar, L. Richard Carley	Synthesis of high-performance analog circuits in ASTRX/OBLX.	IEEE Trans. on CAD of Integrated Circuits and Systems	1996	DBLP DOI BibTeX RDF
1	L. Richard Carley, Georges G. E. Gielen, Rob A. Rutenbar, Willy M. C. Sansen	Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies.	DAC	1996	DBLP DOI BibTeX RDF
1	Bulent Basaran, Rob A. Rutenbar	An O(n) Algorithm for Transistor Stacking with Performance Constraints.	DAC	1996	DBLP DOI BibTeX RDF
1	Prabir C. Maulik, L. Richard Carley, Rob A. Rutenbar	Integer programming based topology selection of cell-level analog circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
1	Jitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar	Testability-oriented channel routing.	VLSI Design	1995	DBLP DOI BibTeX RDF	IC testing quality, testability-oriented channel routing, IC layout modification, test escape probability, iterative channel routing tool, fault undetectability, WrenTR, fault diagnosis, integrated circuit testing, design for testability, fault detectability, network routing, circuit layout CAD, bridging fault, circuit optimisation, integrated circuit layout, design strategies, yield loss, integrated circuit yield
1	Sudip K. Nag, Rob A. Rutenbar	Performance-driven simultaneous place and route for island-style FPGAs.	ICCAD	1995	DBLP DOI BibTeX RDF	Xilinx 4000-series FPGAs, island-style FPGAs, performance-driven simultaneous placement/routing, place and route tools, FPGAs, field programmable gate arrays, logic CAD, network routing, circuit layout CAD, industrial designs, circuit layout
1	Sudip Nag, Rob A. Rutenbar	Performance-Driven Simultaneous Place and Route for Row-Based FPGAs.	DAC	1994	DBLP DOI BibTeX RDF
1	Emil S. Ochotta, Rob A. Rutenbar, L. Richard Carley	ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits.	DAC	1994	DBLP DOI BibTeX RDF
1	Tamal Mukherjee, L. Richard Carley, Rob A. Rutenbar	Synthesis of manufacturable analog circuits.	ICCAD	1994	DBLP DOI BibTeX RDF
1	Bulent Basaran, Rob A. Rutenbar, L. Richard Carley	Latchup-aware placement and parasitic-bounded routing of custom analog cells.	ICCAD	1993	DBLP DOI BibTeX RDF
1	Dorothy E. Setliff, Rob A. Rutenbar	Knowledge Representation and Reasoning in a Software Synthesis Architecture.	IEEE Trans. Software Eng.	1992	DBLP DOI BibTeX RDF	software synthesis architecture, reasoning strategies, automatic program synthesis architecture, ELF, procedure-level decomposition, synthetic router, data structures, knowledge representation, knowledge representation, computer-aided design, inference mechanisms, automatic programming, circuit layout CAD, design space, VLSI circuits, domain-specific knowledge
1	Prabir C. Maulik, L. Richard Carley, Rob A. Rutenbar	A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis.	DAC	1992	DBLP BibTeX RDF
1	Sujoy Mitra, Sudip Nag, Rob A. Rutenbar, L. Richard Carley	System-level routing of mixed-signal ASICs in WREN.	ICCAD	1992	DBLP DOI BibTeX RDF

Publications of "Rob A. Rutenbar" ( http://dblp.L3S.de/Authors/Rob_A._Rutenbar )