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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 19 occurrences of 12 keywords
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Results
Found 51 publication records. Showing 51 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Rolf Drechsler, Irek Ulidowski, Robert Wille |
Foreword: Special Issue on Reversible Computation.  |
Multiple-Valued Logic and Soft Computing  |
2012 |
DBLP BibTeX RDF |
|
| 1 | Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler |
RevKit: A Toolkit for Reversible Circuit Design. |
Multiple-Valued Logic and Soft Computing |
2012 |
DBLP BibTeX RDF |
|
| 1 | Alexis De Vos, Robert Wille (eds.) |
Reversible Computation - Third International Workshop, RC 2011, Gent, Belgium, July 4-5, 2011. Revised Papers |
RC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler |
Synthesis of reversible circuits with minimal lines for large functions. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mathias Soeken, Robert Wille, Rolf Drechsler |
Eliminating invariants in UML/OCL models. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Robert Wille, Mathias Soeken, Rolf Drechsler |
Debugging of inconsistent UML/OCL models. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Robert Wille, Rolf Drechsler, Christof Osewold, Alberto García Ortiz |
Automatic design of low-power encoders using reversible circuit synthesis. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Kenichi Morita, Robert Wille |
Design of Reversible and Quantum Circuits (Dagstuhl Seminar 11502). |
Dagstuhl Reports |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler |
Debugging reversible circuits. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Hongyan Zhang, Rolf Drechsler |
ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hongyan Zhang, Robert Wille, Rolf Drechsler |
Improved Fault Diagnosis for Reversible Circuits. |
Asian Test Symposium |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rolf Drechsler, Alexander Finder, Robert Wille |
Improving ESOP-Based Synthesis of Reversible Logic Using Evolutionary Algorithms. |
EvoApplications |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mathias Soeken, Robert Wille, Rolf Drechsler |
Encoding OCL Data Types for SAT-Based Verification of UML/OCL Models. |
TAP |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler |
RevKit: An Open Source Toolkit for the Design of Reversible Circuits. |
RC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sebastian Offermann, Robert Wille, Rolf Drechsler |
Efficient realization of control logic in reversible circuits. |
FDL |
2011 |
DBLP BibTeX RDF |
|
| 1 | Robert Wille, Oliver Keszocze, Rolf Drechsler |
Determining the minimal number of lines for large reversible circuits. |
DATE |
2011 |
DBLP BibTeX RDF |
|
| 1 | Mathias Soeken, Robert Wille, Rolf Drechsler |
Verifying dynamic aspects of UML models. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Rolf Drechsler |
Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic. |
Electr. Notes Theor. Comput. Sci. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Rolf Drechsler |
Synthese reversibler Logik (Synthesizing Reversible Logic). |
it - Information Technology |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Rolf Drechsler |
BDD-Based Synthesis of Reversible Logic. |
Int. J. of Applied Metaheuristic Computing |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Rolf Drechsler |
Towards a Design Flow for Reversible Logic. |
|
2010 |
DOI RDF |
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| 1 | Hans-Jörg Kreowski, Sabine Kuske, Robert Wille |
Graph Transformation Units Guided by a SAT Solver. |
ICGT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler |
Enhancing debugging of multiple missing control errors in reversible logic. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
boolean satisfiablity (SAT), debugging, reversible logic |
| 1 | Robert Wille, Mathias Soeken, Rolf Drechsler |
Reducing the number of lines in reversible circuits. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
optimization, quantum computation, reversible logic |
| 1 | Stefan Frehse, Robert Wille, Rolf Drechsler |
Efficient Simulation-Based Debugging of Reversible Logic. |
ISMVL |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | D. Michael Miller, Robert Wille, Rolf Drechsler |
Reducing Reversible Circuit Cost by Adding Lines. |
ISMVL |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Sebastian Offermann, Rolf Drechsler |
SyReC: A Programming Language for Synthesis of Reversible Circuits. |
FDL |
2010 |
DBLP BibTeX RDF |
|
| 1 | Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler |
Verifying UML/OCL models using Boolean satisfiability. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
Synthesizing multiplier in reversible logic. |
DDECS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
Window optimization of reversible and quantum circuits. |
DDECS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille |
Towards a design flow for reversible logic. |
|
2009 |
RDF |
|
| 1 | Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
Exact Synthesis of Elementary Quantum Gate Circuits. |
Multiple-Valued Logic and Soft Computing |
2009 |
DBLP BibTeX RDF |
|
| 1 | D. Michael Miller, Robert Wille, Gerhard W. Dueck |
Synthesizing Reversible Circuits for Irreversible Functions. |
DSD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler |
Contradictory antecedent debugging in bounded model checking. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
formal verification, debugging, bounded model checking, psl |
| 1 | Robert Wille, Rolf Drechsler |
BDD-based synthesis of reversible logic for large functions. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
synthesis, decision diagrams, reversible logic, quantum logic |
| 1 | André Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler |
Evaluation of Cardinality Constraints on SMT-Based Debugging. |
ISMVL |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler |
Equivalence Checking of Reversible Circuits. |
ISMVL |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler |
SMT-based stimuli generation in the SystemC Verification library. |
FDL |
2009 |
DBLP BibTeX RDF |
|
| 1 | Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
Reversible Logic Synthesis with Output Permutation. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler |
Debugging of Toffoli networks. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Robert Wille |
Ein Entwurfsablauf für Reversible Schaltkreise. |
Ausgezeichnete Informatikdissertationen |
2009 |
DBLP BibTeX RDF |
|
| 1 | Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler |
Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability. |
ISVLSI |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler |
Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler |
RevLib: An Online Resource for Reversible Functions and Reversible Circuits. |
ISMVL |
2008 |
DBLP DOI BibTeX RDF |
Benchmarks, Synthesis, Reversible Logic |
| 1 | Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. |
ISMVL |
2008 |
DBLP DOI BibTeX RDF |
Synthesis, Boolean Satisfiability, Reversible Logic |
| 1 | Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler |
Contradiction Analysis for Constraint-based Random Simulation. |
FDL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große |
Quantified Synthesis of Reversible Logic. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler |
SWORD: A SAT like prover using word level information. |
VLSI-SoC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Daniel Große |
Fast exact Toffoli network synthesis of reversible logic. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kevin Bolding, Sen-Ching Cheung, Sung-Eun Choi, Carl Ebeling, Soha Hassoun, Ton Anh Ngo, Robert Wille |
The chaos router chip: design and implementation of an adaptive router. |
VLSI |
1993 |
DBLP BibTeX RDF |
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