Search results for "Roger D. Chamberlain"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jeremy D. Buhler, Kunal Agrawal, Peng Li, Roger D. Chamberlain	Efficient deadlock avoidance for streaming computation with filtering.	PPOPP	2012	DBLP DOI BibTeX RDF
1	John Meier, Christopher Gill, Roger D. Chamberlain	Towards More Effective Spectrum Use Based on Memory Allocation Models.	COMPSAC	2011	DBLP DOI BibTeX RDF
1	Lin Ma, Roger D. Chamberlain, Jeremy D. Buhler, Mark A. Franklin	Bloom Filter Performance on Graphics Engines.	ICPP	2011	DBLP DOI BibTeX RDF
1	Joseph M. Lancaster, E. F. Berkley Shands, Jeremy D. Buhler, Roger D. Chamberlain	TimeTrial: A low-impact performance profiler for streaming data applications.	ASAP	2011	DBLP DOI BibTeX RDF
1	Shobana Padmanabhan, Yixin Chen, Roger D. Chamberlain	Optimal design-space exploration of streaming applications.	ASAP	2011	DBLP DOI BibTeX RDF
1	Joseph M. Lancaster, Joseph G. Wingbermuehle, Roger D. Chamberlain	Asking for Performance: Exploiting Developer Intuition to Guide Instrumentation with TimeTrial.	HPCC	2011	DBLP DOI BibTeX RDF
1	Michael J. Hall, Viktor Gruev, Roger D. Chamberlain	Noise analysis of a current-mode read circuit for sensing magnetic tunnel junction resistance.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Joseph M. Lancaster, Joseph G. Wingbermuehle, Jonathan C. Beard, Roger D. Chamberlain	Crossing Boundaries in TimeTrial: Monitoring Communications across Architecturally Diverse Computing Platforms.	EUC	2011	DBLP DOI BibTeX RDF
1	Roger D. Chamberlain, Mark A. Franklin, Eric J. Tyson, James H. Buckley, Jeremy Buhler, Greg Galloway, Saurabh Gayen, Michael J. Hall, E. F. Berkley Shands, Naveen Singla	Auto-Pipe: Streaming Applications on Architecturally Diverse Systems.	IEEE Computer	2010	DBLP DOI BibTeX RDF	Auto-Pipe, Software engineering, Processor architectures, Multicore processors, Computer systems organization
1	Roger D. Chamberlain, Joseph M. Lancaster	Better Languages for More Effective Designing.	ERSA	2010	DBLP BibTeX RDF
1	Roger D. Chamberlain, Jeremy Buhler, Mark A. Franklin, James H. Buckley	Application-guided tool development for architecturally diverse computation.	SAC	2010	DBLP DOI BibTeX RDF	application development tools, approximate text search, computational astrophysics, encryption, computational biology, Monte Carlo simulation, computational finance
1	Peng Li, Kunal Agrawal, Jeremy Buhler, Roger D. Chamberlain, Joseph M. Lancaster	Deadlock-avoidance for streaming applications with split-join structure: Two case studies.	ASAP	2010	DBLP DOI BibTeX RDF
1	Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain	Design of throughput-optimized arrays from recurrence abstractions.	ASAP	2010	DBLP DOI BibTeX RDF
1	Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain	Rapid RNA Folding: Analysis and Acceleration of the Zuker Recurrence.	FCCM	2010	DBLP DOI BibTeX RDF
1	Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain	Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, dynamic programming, systolic array, throughput optimization, recurrences
1	Peng Li, Kunal Agrawal, Jeremy Buhler, Roger D. Chamberlain	Deadlock avoidance for streaming computations with filtering.	SPAA	2010	DBLP DOI BibTeX RDF	architecturally diverse platforms, dataflow, data filtering
1	Narayan Ganesan, Roger D. Chamberlain, Jeremy Buhler, Michela Taufer	Accelerating HMMER on GPUs by implementing hybrid data and task parallelism.	BCB	2010	DBLP DOI BibTeX RDF
1	Joseph M. Lancaster, Jeremy Buhler, Roger D. Chamberlain	Acceleration of ungapped extension in Mercury BLAST.	Microprocessors and Microsystems - Embedded Hardware Design	2009	DBLP DOI BibTeX RDF
1	Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain	Optimal runtime reconfiguration strategies for systolic arrays.	FPL	2009	DBLP DOI BibTeX RDF
1	Roger D. Chamberlain, Narayan Ganesan	Sorting on architecturally diverse computer systems.	SC-HPRCTA	2009	DBLP DOI BibTeX RDF	architecturally diverse systems, field-programmable gate arrays, sorting, reconfigurable hardware
1	Octav Chipara, Christopher Brooks, Sangeeta Bhattacharya, Chenyang Lu, Roger D. Chamberlain, Gruia-Catalin Roman, Thomas C. Bailey	Poster abstract: Reliable data collection from mobile users for real-time clinical monitoring.	IPSN	2009	DBLP DOI BibTeX RDF
1	Joseph M. Lancaster, Jeremy D. Buhler, Roger D. Chamberlain	Efficient runtime performance monitoring of FPGA-based applications.	SoCC	2009	DBLP DOI BibTeX RDF
1	Roger D. Chamberlain, Joseph M. Lancaster, Ron K. Cytron	Visions for application development on hybrid computing systems.	Parallel Computing	2008	DBLP DOI BibTeX RDF
1	Roger D. Chamberlain, Joseph M. Lancaster, Ron K. Cytron	Visions for application development on hybrid computing systems.	Parallel Computing	2008	DBLP DOI BibTeX RDF
1	Arpith C. Jacob, Joseph M. Lancaster, Jeremy Buhler, Brandon Harris, Roger D. Chamberlain	Mercury BLASTP: Accelerating Protein Sequence Alignment.	TRETS	2008	DBLP DOI BibTeX RDF	Bioinformatics, biological sequence alignment
1	Praveen Krishnamurthy, Roger D. Chamberlain	Analytic performance models for bounded queueing systems.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Joseph M. Lancaster, Ron Cytron, Roger D. Chamberlain	Understanding the performance of streaming applications deployed on hybrid systems.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Arpith C. Jacob, Jeremy Buhler, Roger D. Chamberlain	Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAs.	ASAP	2008	DBLP DOI BibTeX RDF
1	Praveen Krishnamurthy, Jeremy Buhler, Roger D. Chamberlain, Mark A. Franklin, Kwame Gyang, Arpith C. Jacob, Joseph M. Lancaster	Biosequence Similarity Search on the Mercury System.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	comparative annotation, biosequence, DNA sequencing
1	Brandon Harris, Arpith C. Jacob, Joseph M. Lancaster, Jeremy Buhler, Roger D. Chamberlain	A Banded Smith-Waterman FPGA Accelerator for Mercury BLASTP.	FPL	2007	DBLP DOI BibTeX RDF
1	Roger D. Chamberlain, Mark A. Franklin, Eric J. Tyson, Jeremy Buhler, Saurabh Gayen, Patrick Crowley, James H. Buckley	Application development on hybrid systems.	SC	2007	DBLP DOI BibTeX RDF	gamma ray astronomy, performance modeling, hybrid systems, hardware/software co-design
1	Arpith C. Jacob, Joseph M. Lancaster, Jeremy D. Buhler, Roger D. Chamberlain	Preliminary results in accelerating profile HMM search on FPGAs.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Saurabh Gayen, Eric J. Tyson, Mark A. Franklin, Roger D. Chamberlain	A Federated Simulation Environment for Hybrid Systems.	PADS	2007	DBLP DOI BibTeX RDF
1	Arpith C. Jacob, Joseph M. Lancaster, Jeremy Buhler, Roger D. Chamberlain	FPGA-accelerated seed generation in Mercury BLASTP.	FCCM	2007	DBLP DOI BibTeX RDF
1	Richard Hough, Praveen Krishnamurthy, Roger D. Chamberlain, Ron K. Cytron, John W. Lockwood, Jason E. Fritts	Empirical performance assessment using soft-core processors on reconfigurable hardware.	Experimental Computer Science	2007	DBLP DOI BibTeX RDF
1	Scott J. Friedman, Praveen Krishnamurthy, Roger D. Chamberlain, Ron K. Cytron, Jason E. Fritts	Dusty caches for reference counting garbage collection.	SIGARCH Computer Architecture News	2006	DBLP DOI BibTeX RDF
1	Shobana Padmanabhan, Ron K. Cytron, Roger D. Chamberlain, John W. Lockwood	Automatic application-specific microarchitecture reconfiguration.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Gary Stiehr, Roger D. Chamberlain	Improving cluster utilization through intelligent processor sharing.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Roger D. Chamberlain, Ron K. Cytron, Jason E. Fritts, John W. Lockwood	Vision for liquid architecture.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Arpith C. Jacob, Brandon Harris, Jeremy Buhler, Roger D. Chamberlain, Young H. Cho	Scalable Softcore Vector Processor for Biosequence Applications.	FCCM	2006	DBLP DOI BibTeX RDF
1	Rahul P. Maddimsetty, Jeremy Buhler, Roger D. Chamberlain, Mark A. Franklin, Brandon Harris	Accelerator design for protein sequence HMM search.	ICS	2006	DBLP DOI BibTeX RDF	protein motif, hidden Markov model, HMMER
1	Shobana Padmanabhan, Phillip H. Jones, David V. Schuehler, Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang, Roger D. Chamberlain, Ron Cytron, Jason E. Fritts, John W. Lockwood	Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures.	International Journal of Parallel Programming	2005	DBLP DOI BibTeX RDF	cycle-accurate hardware profiling, performance, architecture, Reconfigurable
1	Roger D. Chamberlain, Mark A. Franklin, Praveen Krishnamurthy, Abhijit Mahajan	VLSI Photonic Ring Multicomputer Interconnect: Architecture and Signal Processing Performance.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	VLSI photonics, signal processing performance, multicomputer interconnect architecture, optical interconnect
1	Roger D. Chamberlain, John W. Lockwood, Saurabh Gayen, Richard Hough, Phillip H. Jones	Use of a Soft-Core Processor in a Hardware/Software Codesign Laboratory.	MSE	2005	DBLP DOI BibTeX RDF
1	Qiong Zhang, Roger D. Chamberlain, Ronald S. Indeck, Benjamin M. West, Jason White	Massively Parallel Data Mining Using Reconfigurable Hardware: Approximate String Matching.	IPDPS	2004	DBLP DOI BibTeX RDF
1	Praveen Krishnamurthy, Jeremy Buhler, Roger D. Chamberlain, Mark A. Franklin, Kwame Gyang, Joseph M. Lancaster	Biosequence Similarity Search on the Mercury System.	ASAP	2004	DBLP DOI BibTeX RDF
1	Mark A. Franklin, Roger D. Chamberlain, Michael Henrichs, E. F. Berkley Shands, Jason White	An Architecture for Fast Processing of Large Unstructured Data Sets.	ICCD	2004	DBLP DOI BibTeX RDF
1	Roger D. Chamberlain, Eric Hemmeter, Robert Morley, Jason White	Modeling the Power Consumption of Audio Signal Processing Computations Using Customized Numerical Representations.	Annual Simulation Symposium	2003	DBLP DOI BibTeX RDF	numerical representation, power consumption, audio signal processing
1	Praveen Krishnamurthy, Mark A. Franklin, Roger D. Chamberlain	Dynamic Reconfiguration of an Optical Interconnect.	Annual Simulation Symposium	2003	DBLP DOI BibTeX RDF
1	Roger D. Chamberlain, Mark A. Franklin, Ch'ng Shi Baw	Gemini: An Optical Interconnection Network for Parallel Processing.	IEEE Trans. Parallel Distrib. Syst.	2002	DBLP DOI BibTeX RDF	fair scheduling protocols, performance evaluation, multiprocessor interconnection networks, Optical communication
1	Jason E. Fritts, Roger D. Chamberlain	Breaking the Memory Bottleneck with an Optical Data Path.	Annual Simulation Symposium	2002	DBLP DOI BibTeX RDF	bandwidth bottleneck, processor-memory gap, performance evaluation, media processing, optical bus
1	Roger D. Chamberlain, Ch'ng Shi Baw, Mark A. Franklin, Christopher Hackmann, Praveen Krishnamurthy, Abhijit Mahajan, Michael Wrighton	Evaluating the Performance of Photonic Interconnection Networks.	Annual Simulation Symposium	2002	DBLP DOI BibTeX RDF	photonics, interconnection networks, multiprocessor systems, optics
1	Michael D. DeVore, Roger D. Chamberlain, George Engel, Joseph A. O'Sullivan, Mark A. Franklin	Tradeoffs Between Quality of Results and Resource Consumption in a Recognition System.	ASAP	2002	DBLP DOI BibTeX RDF
1	Roger D. Chamberlain, Mark A. Franklin, Praveen Krishnamurthy	Optical Network Reconfiguration for Signal Processing Applications.	ASAP	2002	DBLP DOI BibTeX RDF
1	Bradley L. Noble, J. Cris Wade, Roger D. Chamberlain	Performance Predictions for Speculative, Synchronous, VLSI Logic Simulation.	Annual Simulation Symposium	2001	DBLP DOI BibTeX RDF
1	Roger D. Chamberlain, Mark A. Franklin, Abhijit Mahajan	VLSI Photonic Ring Interconnect for Embedded Multicomputers: Architecture and Performance.	ISCA PDCS	2001	DBLP BibTeX RDF
1	Bradley L. Noble, Roger D. Chamberlain	Analytic performance model for speculative, synchronous, discrete-event simulation.	PADS	2000	DBLP DOI BibTeX RDF
1	Ch'ng Shi Baw, Roger D. Chamberlain, Mark A. Franklin	Fair Scheduling in an Optical Interconnection Network. (PDF / PS)	MASCOTS	1999	DBLP DOI BibTeX RDF	Fair Scheduling, Optical Interconnection Networks
1	Bradley L. Noble, Roger D. Chamberlain	Performance Model for Speculative Simulation using Predictive Optimism. (PDF / PS)	HICSS	1999	DBLP DOI BibTeX RDF
1	Gregory D. Peterson, Roger D. Chamberlain	Parallel application performance in a shared resource environment.	Distributed Systems Engineering	1996	DBLP DOI BibTeX RDF
1	George Varghese, Roger D. Chamberlain, William E. Weihl	Deriving Global Virtual Time Algorithms from Conservative Simulation Protocols.	Inf. Process. Lett.	1995	DBLP DOI BibTeX RDF
1	Roger D. Chamberlain	Parallel Logic Simulation of VLSI Systems.	DAC	1995	DBLP DOI BibTeX RDF
1	Roger D. Chamberlain, Gregory D. Peterson, Mark A. Franklin, Michael A. Province	Genetic epidemiology, parallel algorithms, and workstation networks.	HICSS	1995	DBLP DOI BibTeX RDF	genetic epidemiology, Gemini/Almini library, routines, optimization routines, cost-effective parallel implementations, genetic epidemiological applications, performance, parallel algorithms, parallel algorithms, optimisation, local area networks, local area network, software performance evaluation, software libraries, subroutines, genetics, biology computing, cost-effective, workstation networks, nonlinear optimization problems, networked workstations
1	Bradley L. Noble, Gregory D. Peterson, Roger D. Chamberlain	Performance of synchronous parallel discrete-event simulation.	HICSS	1995	DBLP DOI BibTeX RDF	synchronous parallel discrete-event simulation algorithms, global clock algorithm, conservative lookahead algorithm, execution platforms, shared computational resources, torus topology, performance, parallel algorithms, synchronization, resource allocation, discrete event simulation, local area networks, queueing theory, network topology, synchronisation, shared-memory multiprocessor, shared memory systems, queueing network, software performance evaluation, granularity, workstation network, load imbalance, speculative computation
1	Gregory D. Peterson, Roger D. Chamberlain	Stealing cycles: Can we get along?	HICSS	1995	DBLP DOI BibTeX RDF	shared networked workstations, cost-effective parallel computing, policy questions, performance levels, workstation user, performance evaluation, parallel processing, distributed processing, performance models, processor scheduling, workstations, parallel application, computational resources, multi-access systems, multi-user system
1	Mary L. Bailey, Jack V. Briner Jr., Roger D. Chamberlain	Parallel Logic Simulation of VLSI Systems.	ACM Comput. Surv.	1994	DBLP DOI BibTeX RDF
1	Gregory D. Peterson, Roger D. Chamberlain	Performance of a Globally-Clocked Parallel Simulator.	ICPP	1993	DBLP BibTeX RDF
1	Roger D. Chamberlain, Mark A. Franklin	Performance Effects of Synchronization in Parallel Processors.	SPDP	1993	DBLP BibTeX RDF
1	Gregory D. Peterson, Roger D. Chamberlain	Exploiting lookahead in synchronous parallel simulation.	Winter Simulation Conference	1993	DBLP DOI BibTeX RDF
1	Ellen E. Witte, Roger D. Chamberlain, Mark A. Franklin	Parallel Simulated Annealing using Speculative Computation.	IEEE Trans. Parallel Distrib. Syst.	1991	DBLP DOI BibTeX RDF	problem independent algorithm, parallel simulated annealingalgorithm, serial decision sequence, task assignment problem, parallel algorithms, concurrency, simulated annealing, processors, hypercube multiprocessor, speculative computation
1	Roger D. Chamberlain, Mark A. Franklin	Analysis of Parallel Mixed-Mode Simulation Algorithms.	IPPS	1991	DBLP BibTeX RDF
1	Ellen E. Witte, Roger D. Chamberlain, Mark A. Franklin	Parallel Simulated Annealing Using Speculative Computation.	ICPP	1990	DBLP BibTeX RDF
1	Roger D. Chamberlain, Mark A. Franklin	Collecting Data About Logic Simulation.	IEEE Trans. on CAD of Integrated Circuits and Systems	1986	DBLP DOI BibTeX RDF
1	Kenneth F. Wong, Mark A. Franklin, Roger D. Chamberlain, B. L. Shing	Statistics on logic simulation.	DAC	1986	DBLP DOI BibTeX RDF

Publications of "Roger D. Chamberlain" ( http://dblp.L3S.de/Authors/Roger_D._Chamberlain )