| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Rolf Drechsler, Irek Ulidowski, Robert Wille |
Foreword: Special Issue on Reversible Computation.  |
Multiple-Valued Logic and Soft Computing  |
2012 |
DBLP BibTeX RDF |
|
| 1 | Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler |
RevKit: A Toolkit for Reversible Circuit Design. |
Multiple-Valued Logic and Soft Computing |
2012 |
DBLP BibTeX RDF |
|
| 1 | Cecilia Di Chio, Alexandros Agapitos, Stefano Cagnoni, Carlos Cotta, Francisco Fernández de Vega, Gianni A. Di Caro, Rolf Drechsler, Anikó Ekárt, Anna Isabel Esparcia-Alcázar, Muddassar Farooq, William B. Langdon, Juan J. Merelo Guervós, Mike Preuss, Hendrik Richter, Sara Silva, Anabela Simões, Giovanni Squillero, Ernesto Tarantino, Andrea Tettamanzi, Julian Togelius, Neil Urquhart, Sima Uyar, Georgios N. Yannakakis (eds.) |
Applications of Evolutionary Computation - EvoApplications 2012: EvoCOMNET, EvoCOMPLEX, EvoFIN, EvoGAMES, EvoHOT, EvoIASP, EvoNUM, EvoPAR, EvoRISK, EvoSTIM, and EvoSTOC, Málaga, Spain, April 11-13, 2012, Proceedings |
EvoApplications |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler |
Synthesis of reversible circuits with minimal lines for large functions. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Finn Haedicke, Daniel Große, Rolf Drechsler |
A guiding coverage metric for formal verification. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Mathias Soeken, Robert Wille, Rolf Drechsler |
Eliminating invariants in UML/OCL models. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Robert Wille, Mathias Soeken, Rolf Drechsler |
Debugging of inconsistent UML/OCL models. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Robert Wille, Rolf Drechsler, Christof Osewold, Alberto García Ortiz |
Automatic design of low-power encoders using reversible circuit synthesis. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Stephan Eggersglüß, Rolf Drechsler |
Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler |
Effective Robustness Analysis Using Bounded Model Checking Techniques. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler |
Debugging reversible circuits. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Hongyan Zhang, Rolf Drechsler |
ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hongyan Zhang, Robert Wille, Rolf Drechsler |
Improved Fault Diagnosis for Reversible Circuits. |
Asian Test Symposium |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Cecilia Di Chio, Anthony Brabazon, Gianni A. Di Caro, Rolf Drechsler, Muddassar Farooq, Jörn Grahl, Gary Greenfield, Christian Prins, Juan Romero, Giovanni Squillero, Ernesto Tarantino, Andrea Tettamanzi, Neil Urquhart, A. Sima Etaner-Uyar (eds.) |
Applications of Evolutionary Computation - EvoApplications 2011: EvoCOMNET, EvoFIN, EvoHOT, EvoMUSART, EvoSTIM, and EvoTRANSLOG, Torino, Italy, April 27-29, 2011, Proceedings, Part II |
EvoApplications |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rolf Drechsler, Alexander Finder, Robert Wille |
Improving ESOP-Based Synthesis of Reversible Logic Using Evolutionary Algorithms. |
EvoApplications |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler |
Simulation-based equivalence checking between SystemC models at different levels of abstraction. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mathias Soeken, Robert Wille, Rolf Drechsler |
Encoding OCL Data Types for SAT-Based Verification of UML/OCL Models. |
TAP |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler |
RevKit: An Open Source Toolkit for the Design of Reversible Circuits. |
RC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Marc Michael, Daniel Große, Rolf Drechsler |
Analyzing dependability measures at the Electronic System Level. |
FDL |
2011 |
DBLP BibTeX RDF |
|
| 1 | Sebastian Offermann, Robert Wille, Rolf Drechsler |
Efficient realization of control logic in reversible circuits. |
FDL |
2011 |
DBLP BibTeX RDF |
|
| 1 | Robert Wille, Oliver Keszocze, Rolf Drechsler |
Determining the minimal number of lines for large reversible circuits. |
DATE |
2011 |
DBLP BibTeX RDF |
|
| 1 | Stephan Eggersglüß, Rolf Drechsler |
As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization. |
DATE |
2011 |
DBLP BibTeX RDF |
|
| 1 | Mathias Soeken, Robert Wille, Rolf Drechsler |
Verifying dynamic aspects of UML models. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohamed Bawadekji, Daniel Große, Rolf Drechsler |
TLM protocol compliance checking at the Electronic System Level. |
DDECS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler |
Automatic property generation for the formal verification of bus bridges. |
DDECS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Rolf Drechsler |
Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic. |
Electr. Notes Theor. Comput. Sci. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Tille, Stephan Eggersglüß, Rolf Drechsler |
Incremental Solving Techniques for SAT-based ATPG. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ulrich Kühne, Daniel Große, Rolf Drechsler |
Towards Fully Automatic Synthesis of Embedded Software. |
Embedded Systems Letters |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler |
Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits). |
it - Information Technology |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Rolf Drechsler |
Synthese reversibler Logik (Synthesizing Reversible Logic). |
it - Information Technology |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Rolf Drechsler |
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. |
J. Electronic Testing |
2010 |
DBLP BibTeX RDF |
|
| 1 | Robert Wille, Rolf Drechsler |
BDD-Based Synthesis of Reversible Logic. |
Int. J. of Applied Metaheuristic Computing |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Rolf Drechsler |
Quality-Driven SystemC Design |
|
2010 |
RDF |
|
| 1 | Robert Wille, Rolf Drechsler |
Towards a Design Flow for Reversible Logic. |
|
2010 |
DOI RDF |
|
| 1 | Frank Rogin, Rolf Drechsler |
Debugging at the Electronic System Level. |
|
2010 |
DOI RDF |
|
| 1 | Daniel Große, Hoang M. Le, Rolf Drechsler |
Proving transaction and system-level properties of untimed SystemC TLM designs. |
MEMOCODE |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler |
RobuCheck: A Robustness Checker for Digital Circuits. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hoang M. Le, Daniel Große, Rolf Drechsler |
Towards analyzing functional coverage in SystemC TLM property checking. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler |
Enhancing debugging of multiple missing control errors in reversible logic. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
boolean satisfiablity (SAT), debugging, reversible logic |
| 1 | Robert Wille, Mathias Soeken, Rolf Drechsler |
Reducing the number of lines in reversible circuits. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
optimization, quantum computation, reversible logic |
| 1 | Alexander Finder, Rolf Drechsler |
An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions. |
ISMVL |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefan Frehse, Robert Wille, Rolf Drechsler |
Efficient Simulation-Based Debugging of Reversible Logic. |
ISMVL |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | D. Michael Miller, Robert Wille, Rolf Drechsler |
Reducing Reversible Circuit Cost by Adding Lines. |
ISMVL |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler |
Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. |
European Test Symposium |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Sebastian Offermann, Rolf Drechsler |
SyReC: A Programming Language for Synthesis of Reversible Circuits. |
FDL |
2010 |
DBLP BibTeX RDF |
|
| 1 | Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler |
Verifying UML/OCL models using Boolean satisfiability. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | André Sülflow, Görschwin Fey, Rolf Drechsler |
Using QBF to increase accuracy of SAT-based debugging. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | André Sülflow, Rolf Drechsler |
Automatic Fault Localization for Programmable Logic Controllers. |
FORMS/FORMAT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hoang M. Le, Daniel Große, Rolf Drechsler |
Automatic Fault Localization for SystemC TLM Designs. |
MTV |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey, André Sülflow, Rolf Drechsler |
Towards Unifying Localization and Explanation for Automated Debugging. |
MTV |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Rolf Drechsler, Görschwin Fey |
Formal verification meets robustness checking - Techniques and challenges. |
DDECS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefan Frehse, Görschwin Fey, Rolf Drechsler |
A better-than-worst-case robustness measure. |
DDECS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
Synthesizing multiplier in reversible logic. |
DDECS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
Window optimization of reversible and quantum circuits. |
DDECS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler |
Polynomial datapath optimization using constraint solving and formal modelling. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke |
Advanced verification by automatic property generation. |
IET Computers & Digital Techniques |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rüdiger Ebendt, Rolf Drechsler |
Weighted A* search - unifying view and application. |
Artif. Intell. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
Exact Synthesis of Elementary Quantum Gate Circuits. |
Multiple-Valued Logic and Soft Computing |
2009 |
DBLP BibTeX RDF |
|
| 1 | Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille |
Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). |
it - Information Technology |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille |
Test Pattern Generation using Boolean Proof Engines. |
|
2009 |
DOI RDF |
|
| 1 | Rolf Drechsler, Tommi A. Junttila, Ilkka Niemelä |
Non-Clausal SAT and ATPG. |
Handbook of Satisfiability |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler |
WoLFram- A Word Level Framework for Formal Verification. |
IEEE International Workshop on Rapid System Prototyping |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
Speeding up SAT-Based ATPG Using Dynamic Clause Activation. |
Asian Test Symposium |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler |
Robustness Check for Multiple Faults Using Formal Techniques. |
DSD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler |
Contradictory antecedent debugging in bounded model checking. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
formal verification, debugging, bounded model checking, psl |
| 1 | Robert Wille, Rolf Drechsler |
BDD-based synthesis of reversible logic for large functions. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
synthesis, decision diagrams, reversible logic, quantum logic |
| 1 | Görschwin Fey, André Sülflow, Rolf Drechsler |
Computing bounds for fault tolerance using formal techniques. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
fault tolerance, formal verification, SAT |
| 1 | André Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler |
Evaluation of Cardinality Constraints on SMT-Based Debugging. |
ISMVL |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler |
Equivalence Checking of Reversible Circuits. |
ISMVL |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephan Eggersglüß, Rolf Drechsler |
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques. |
European Test Symposium |
2009 |
DBLP DOI BibTeX RDF |
ATPG, SAT, Delay Test, Boolean Satisfiability, Dynamic Learning |
| 1 | Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler |
SMT-based stimuli generation in the SystemC Verification library. |
FDL |
2009 |
DBLP BibTeX RDF |
|
| 1 | Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
Reversible Logic Synthesis with Output Permutation. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ulrich Kühne, Daniel Große, Rolf Drechsler |
Property analysis and design understanding. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Christian Genz, Rolf Drechsler |
Overcoming limitations of the SystemC data introspection. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler |
Increasing the accuracy of SAT-based debugging. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler |
Debugging of Toffoli networks. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Rüdiger Ebendt, Rolf Drechsler |
Approximate BDD Minimization by Weighted A. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Hoang M. Le, Rolf Drechsler |
Induction-Based Formal Verification of SystemC TLM Designs. |
MTV |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Tille, Rolf Drechsler |
A fast untestability proof for SAT-based ATPG. |
DDECS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Frank Rogin, Rolf Drechsler, Steffen Rülke |
Automatic debugging of System-on-a-Chip designs. |
SoCC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler |
Timing Arc based logic analysis for false noise reduction. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler |
On the construction of small fully testable circuits with low depth. |
Microprocessors and Microsystems - Embedded Hardware Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sean Safarpour, Andreas G. Veneris, Rolf Drechsler |
Improved SAT-based Reachability Analysis with Observability Don't Cares. |
JSAT |
2008 |
DBLP BibTeX RDF |
|
| 1 | Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa |
Logic Minimization and Testability of 2-SPP Networks. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Ulrich Kühne, Rolf Drechsler |
Analyzing Functional Coverage in Bounded Model Checking. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler |
Automatic Fault Localization for Property Checking. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille |
On Acceleration of SAT-Based ATPG for Industrial Designs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sebastian Kinder, Rolf Drechsler |
Modeling and proving functional completeness in formal verification of counting heads. |
STTT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey, Rolf Drechsler |
Robustness and usability in modern design flows. |
|
2008 |
RDF |
|
| 1 | Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler |
Adaptive Branch and Bound Using SAT to Estimate False Crosstalk. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
Crosstalk Analysis, False Noise, STA, SAT Solver |
| 1 | Görschwin Fey, Rolf Drechsler |
A Basis for Formal Robustness Checking. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
Formal Methods, Robustness, Fault models, SAT |
| 1 | Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler |
Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability. |
ISVLSI |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Mario Giacobini, Anthony Brabazon, Stefano Cagnoni, Gianni Di Caro, Rolf Drechsler, Anikó Ekárt, Anna Esparcia-Alcázar, Muddassar Farooq, Andreas Fink, Jon McCormack, Michael O'Neill, Juan Romero, Franz Rothlauf, Giovanni Squillero, Sima Uyar, Shengxiang Yang (eds.) |
Applications of Evolutionary Computing, EvoWorkshops 2008: EvoCOMNET, EvoFIN, EvoHOT, EvoIASP, EvoMUSART, EvoNUM, EvoSTOC, and EvoTransLog, Naples, Italy, March 26-28, 2008. Proceedings |
EvoWorkshops |
2008 |
DBLP BibTeX RDF |
|
| 1 | Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler |
Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler |
Using unsatisfiable cores to debug multiple design errors. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
sat-based debugging, unsatisfiable core, fault localization |
| 1 | Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler |
RevLib: An Online Resource for Reversible Functions and Reversible Circuits. |
ISMVL |
2008 |
DBLP DOI BibTeX RDF |
Benchmarks, Synthesis, Reversible Logic |
| 1 | Stephan Eggersglüß, Rolf Drechsler |
On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults. |
ISMVL |
2008 |
DBLP DOI BibTeX RDF |
Boolean Encodings, ATPG, SAT, Path Delay Faults |
| 1 | Doina Logofatu, Rolf Drechsler |
Comparative Study by Solving the Test Compaction Problem. |
ISMVL |
2008 |
DBLP DOI BibTeX RDF |
Backtracking, Multi-Valued Logic, Test Compaction, Set Cover Problem, Greedy, Don't Cares |
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