Search results for "Roman L. Lysecky"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Arslan Munir, Ann Gordon-Ross, Susan Lysecky, Roman L. Lysecky	Online algorithms for wireless sensor networks dynamic optimization.	CCNC	2012	DBLP DOI BibTeX RDF
1	Ajay Nair, Karthik Shankar, Roman L. Lysecky	Efficient hardware-based nonintrusive dynamic application profiling.	ACM Trans. Embedded Comput. Syst.	2011	DBLP DOI BibTeX RDF
1	Jingqing Mu, Roman L. Lysecky	Profile assisted online system-level performance and power estimation for dynamic reconfigurable embedded systems.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Ashish Shenoy, Jeff Hiner, Susan Lysecky, Roman L. Lysecky, Ann Gordon-Ross	Evaluation of Dynamic Profiling Methodologies for Optimization of Sensor Networks.	Embedded Systems Letters	2010	DBLP DOI BibTeX RDF
1	Rahul Kalra, Roman L. Lysecky	Configuration Locking and Schedulability Estimation for Reduced Reconfiguration Overheads of Reconfigurable Systems.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Jin Sun, Roman L. Lysecky, Karthik Shankar, Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang	Workload capacity considering NBTI degradation in multi-core systems.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Jeff Hiner, Ashish Shenoy, Roman L. Lysecky, Susan Lysecky, Ann Gordon-Ross	Transaction-Level Modeling for Sensor Networks Using SystemC.	SUTC/UMC	2010	DBLP DOI BibTeX RDF	SystemC profiling, simulation, Sensor networks, transaction-level modeling
1	Arslan Munir, Ann Gordon-Ross, Susan Lysecky, Roman L. Lysecky	A lightweight dynamic optimization methodology for wireless sensor networks.	WiMob	2010	DBLP DOI BibTeX RDF
1	Jin Sun, Rui Zheng, Jyothi Velamala, Yu Cao, Roman L. Lysecky, Karthik Shankar, Janet Meiling Wang Roveda	A self-evolving design methodology for power efficient multi-core systems.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Roman L. Lysecky, Frank Vahid	Design and implementation of a MicroBlaze-based warp processor.	ACM Trans. Embedded Comput. Syst.	2009	DBLP DOI BibTeX RDF	soft processor cores, FPGA, dynamic optimization, hardware/software partitioning, configurable logic, Warp processors, just-in-time (JIT) compilation
1	Lance Saldanha, Roman L. Lysecky	Float-to-fixed and fixed-to-float hardware converters for rapid hardware/software partitioning of floating point software applications to static and dynamic fixed point coprocessors.	Design Autom. for Emb. Sys.	2009	DBLP DOI BibTeX RDF
1	Jingqing Mu, Roman L. Lysecky	Autonomous hardware/software partitioning and voltage/frequency scaling for low-power embedded systems.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF
1	Karthik Shankar, Roman L. Lysecky	Non-intrusive dynamic application profiling for multitasked applications.	DAC	2009	DBLP DOI BibTeX RDF	dynamic hardware/software partitioning, profiling, dynamic optimizations, multitasking, real-time embedded systems
1	Roman L. Lysecky	Scalability and Parallel Execution of Warp Processing: Dynamic Hardware/Software Partitioning.	International Journal of Parallel Programming	2008	DBLP DOI BibTeX RDF	Warp processing, Embedded systems, Hardware/software partitioning, Dynamically adaptable systems
1	Frank Vahid, Greg Stitt, Roman L. Lysecky	Warp Processing: Dynamic Translation of Binaries to FPGA Circuits.	IEEE Computer	2008	DBLP DOI BibTeX RDF
1	Ajay Nair, Roman L. Lysecky	Non-intrusive dynamic application profiler for detailed loop execution characterization.	CASES	2008	DBLP DOI BibTeX RDF	nonintrusive, embedded systems, profiling, dynamic optimization
1	Mark Hammerquist, Roman L. Lysecky	Design space exploration for application specific FPGAS in system-on-a-chip designs.	SoCC	2008	DBLP DOI BibTeX RDF
1	Lance Saldanha, Roman L. Lysecky	Hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	floating point to fixed conversion, floating point, fixed point, hardware/software partitioning
1	Roman L. Lysecky, Frank Vahid	A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning	CoRR	2007	DBLP BibTeX RDF
1	Roman L. Lysecky	Low-power warp processor for power efficient high-performance embedded systems.	DATE	2007	DBLP DOI BibTeX RDF	warp processing, embedded systems, low-power, hardware/software partitioning, dynamically adaptable systems
1	Roman L. Lysecky, Greg Stitt, Frank Vahid	Warp Processors.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	FPGA, dynamic optimization, hardware/software codesign, hardware/software partitioning, configurable logic, Warp processors, just-in-time (JIT) compilation
1	David Sheldon, Rakesh Kumar, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky	Conjoining soft-core FPGA processors.	ICCAD	2006	DBLP DOI BibTeX RDF	conjoined processors, parameterized platforms, soft-core processors, FPGAs, customization, tuning
1	David Sheldon, Rakesh Kumar, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen	Application-specific customization of parameterized FPGA soft-core processors.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan	A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation.	FCCM	2005	DBLP DOI BibTeX RDF	standard hardware binary, FPGA, dynamic optimization, system-on-a-chip, platforms, codesign, hardware/software partitioning, configurable logic, Place and route, warp processors, just-in-time (JIT) compilation
1	Roman L. Lysecky, Kris Miller, Frank Vahid, Kees A. Vissers	Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
1	Roman L. Lysecky, Frank Vahid	A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning.	DATE	2005	DBLP DOI BibTeX RDF
1	Chuanjun Zhang, Frank Vahid, Roman L. Lysecky	A self-tuning cache architecture for embedded systems.	ACM Trans. Embedded Comput. Syst.	2004	DBLP DOI BibTeX RDF	on-chip CAD, embedded systems, low power, Cache, configurable, dynamic optimization, low energy, architecture tuning
1	Roman L. Lysecky, Susan Cotterell, Frank Vahid	A fast on-chip profiler memory using a pipelined binary tree.	IEEE Trans. VLSI Syst.	2004	DBLP BibTeX RDF
1	Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan	Dynamic FPGA routing for just-in-time FPGA compilation.	DAC	2004	DBLP DOI BibTeX RDF	FPGA, dynamic optimization, system-on-a-chip, platforms, codesign, hardware/software partitioning, just-in-time compilation, configurable logic, place and route, warp processors
1	Chuanjun Zhang, Frank Vahid, Roman L. Lysecky	A Self-Tuning Cache Architecture for Embedded Systems.	DATE	2004	DBLP DOI BibTeX RDF	on-chip CAD, embedded systems, low power, Cache, configurable, dynamic optimization, low energy, architecture tuning
1	Roman L. Lysecky, Frank Vahid	A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning.	DATE	2004	DBLP DOI BibTeX RDF	FPGA fabric, self-improving chips, synthesis, reconfigurable computing, dynamic optimization, system-on-a-chip, platforms, codesign, Hardware/software partitioning, just-in-time compilation, configurable logic, place and route, warp processors
1	Frank Vahid, Roman L. Lysecky, Chuanjun Zhang, Greg Stitt	Highly configurable platforms for embedded computing systems.	Microelectronics Journal	2003	DBLP DOI BibTeX RDF
1	Greg Stitt, Roman L. Lysecky, Frank Vahid	Dynamic hardware/software partitioning: a first approach.	DAC	2003	DBLP DOI BibTeX RDF	self-improving chips, FPGA, embedded systems, synthesis, dynamic optimization, system-on-a-chip, platforms, codesign, hardware/software partitioning
1	Roman L. Lysecky, Frank Vahid	On-chip logic minimization.	DAC	2003	DBLP DOI BibTeX RDF	on-chip logic minimization, on-chip synthesis, embedded systems, dynamic optimization, system-on-a-chip, logic minimization
1	Roman L. Lysecky, Frank Vahid	A codesigned on-chip logic minimizer.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	embedded CAD, on-chip logic minimization, on-chip synthesis, embedded systems, dynamic optimization, system-on-a-chip, hardware/software codesign, logic minimization
1	Roman L. Lysecky, Frank Vahid	Prefetching for improved bus wrapper performance in cores.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	Bus wrapper, PVCI, VSIA, interfacing, system-on-a-chip, intellectual property, cores, design reuse, on-chip bus
1	Roman L. Lysecky, Susan Cotterell, Frank Vahid	A fast on-chip profiler memory.	DAC	2002	DBLP DOI BibTeX RDF	embedded CAD, platform tuning, embedded systems, low power, profiling, system-on-a-chip, binary tree, adaptive architectures, memory design
1	Greg Stitt, Frank Vahid, Tony Givargis, Roman L. Lysecky	A first-step towards an architecture tuning methodology for low power.	CASES	2000	DBLP DOI BibTeX RDF	parameterized architectures, embedded systems, low-power, system-on-a-chip, cores, tuning
1	Roman L. Lysecky, Frank Vahid, Tony Givargis	Experiments with the Peripheral Virtual Component Interface.	ISSS	2000	DBLP DOI BibTeX RDF	VCI, bus wrappers, interfacing, system-on-a-chip, intellectual property, Cores, on-chip bus
1	Roman L. Lysecky, Frank Vahid, Tony Givargis	Techniques for Reducing Read Latency of Core Bus Wrappers.	DATE	2000	DBLP DOI BibTeX RDF	bus wrapper, interfacing, system-on-a-chip, intellectual property, Cores, design reuse, on-chip bus
1	Roman L. Lysecky, Frank Vahid, Rilesh Patel, Tony Givargis	Pre-Fetching for Improved Core Interfacing. (PDF / PS)	ISSS	1999	DBLP DOI BibTeX RDF	interfacing, system-on-a-chip, intellectual property, Cores, on-chip bus

Publications of "Roman L. Lysecky" ( http://dblp.L3S.de/Authors/Roman_L._Lysecky )