| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Wing Chiu Tam, R. D. (Shawn) Blanton |
SLIDER: Simulation of Layout-Injected Defects for Electrical Responses.  |
IEEE Trans. on CAD of Integrated Circuits and Systems  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yen-Tzu Lin, Osei Poku, R. D. (Shawn) Blanton, Phil Nigh, Peter Lloyd, Vikram Iyengar |
Physically-Aware N-Detect Test. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | R. D. (Shawn) Blanton, Wing Chiu Tam, Xiaochun Yu, Jeffrey E. Nelson, Osei Poku |
Yield Learning Through Physically Aware Diagnosis of IC-Failure Populations. |
IEEE Design & Test of Computers |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yen-Tzu Lin, R. D. (Shawn) Blanton |
METER: Measuring Test Effectiveness Regionally. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Wing Chiu Tam, R. D. (Shawn) Blanton |
Physically-aware analysis of systematic defects in integrated circuits. |
ITC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Bill Eklow, R. D. (Shawn) Blanton (eds.) |
2011 IEEE International Test Conference, ITC 2011, Anaheim, CA, USA, September 20-22, 2011 |
ITC |
2011 |
DBLP BibTeX RDF |
|
| 1 | Wing Chiu Tam, R. D. (Shawn) Blanton |
To DFM or not to DFM? |
DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaochun Yu, R. D. (Shawn) Blanton |
Statistical defect-detection analysis of test sets using readily-available tester data. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Wangyang Zhang, Xin Li, Frank Liu, Emrah Acar, Rob A. Rutenbar, Ronald D. Blanton |
Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sounil Biswas, Ronald D. Blanton |
Reducing Test Execution Cost of Integrated, Heterogeneous Systems Using Continuous Test Data. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Wing Chiu Tam, Ronald D. Blanton |
SLIDER: A fast and accurate defect simulation framework. |
VTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Wing Chiu Tam, R. D. (Shawn) Blanton, Wojciech Maly |
Evaluating yield and testing impact of sub-wavelength lithography. |
VTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaochun Yu, Ronald D. Blanton |
Diagnosis of Integrated Circuits With Multiple Defects of Arbitrary Characteristics. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeffrey E. Nelson, Wing Chiu Tam, Ronald D. Blanton |
Automatic classification of bridge defects. |
ITC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Wing Chiu Tam, Osei Poku, Ronald D. Blanton |
Systematic defect identification through layout snippet clustering. |
ITC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaochun Yu, Ronald D. Blanton |
Estimating defect-type distributions through volume diagnosis and defect behavior attribution. |
ITC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Wing Chiu Tam, Osei Poku, R. D. (Shawn) Blanton |
Automated failure population creation for validating integrated circuit diagnosis methods. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
verification, fault diagnosis, failure analysis |
| 1 | Xin Li, Rob A. Rutenbar, R. D. (Shawn) Blanton |
Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Yen-Tzu Lin, Ronald D. Blanton |
Test effectiveness evaluation through analysis of readily-available tester data. |
ITC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yen-Tzu Lin, Chukwuemeka U. Ezekwe, Ronald D. Blanton |
Physically-Aware N-Detect Test Relaxation. |
VTS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaochun Yu, Yen-Tzu Lin, Wing Chiu Tam, Osei Poku, Ronald D. Blanton |
Controlling DPPM through Volume Diagnosis. |
VTS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sounil Biswas, Ronald D. Blanton |
Maintaining Accuracy of Test Compaction through Adaptive Re-learning. |
VTS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason G. Brown, R. D. (Shawn) Blanton |
Automated Standard Cell Library Analysis for Improved Defect Modeling. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
test generation, diagnosis, fault simulation, fault, defect |
| 1 | Xiaochun Yu, R. D. (Shawn) Blanton |
Multiple defect diagnosis using no assumptions on failing pattern characteristics. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
defect diagnosis, fault isolation, IC testing |
| 1 | Wing Chiu Tam, Osei Poku, R. D. (Shawn) Blanton |
Precise failure localization using automated layout analysis of diagnosis candidates. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
defect localization, physical failure analysis, diagnosis, layout analysis |
| 1 | Sounil Biswas, R. D. (Shawn) Blanton |
Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data. |
VTS |
2008 |
DBLP DOI BibTeX RDF |
pass-fail test data, boolean minimization, minimum constrained subset cover, Mixed-signal test, test compaction |
| 1 | Sounil Biswas, Ronald D. Blanton |
Improving the Accuracy of Test Compaction through Adaptive Test Update. |
ITC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaochun Yu, Ronald D. Blanton |
An Effective and Flexible Multiple Defect Diagnosis Methodology Using Error Propagation Analysis. |
ITC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yen-Tzu Lin, Osei Poku, Ronald D. Blanton, Phil Nigh, Peter Lloyd, Vikram Iyengar |
Evaluating the Effectiveness of Physically-Aware N-Detect Test using Real Silicon. |
ITC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason G. Brown, Brian Taylor, Ronald D. Blanton, Larry T. Pileggi |
Automated Testability Enhancements for Logic Brick Libraries. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yen-Tzu Lin, Osei Poku, Naresh K. Bhatti, Ronald D. Blanton |
Physically-Aware N-Detect Test Pattern Selection. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi |
Specification Test Compaction for Analog Circuits and MEMS |
CoRR |
2007 |
DBLP BibTeX RDF |
|
| 1 | Jason G. Brown, R. D. (Shawn) Blanton |
A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology. |
J. Electronic Testing |
2007 |
DBLP DOI BibTeX RDF |
fault diagnostic accuracy, nanofabrication, regular architectures, nanoFabric, fault diagnosis, logic testing, reconfigurability, integrated circuit testing, fault coverage, nanoelectronics, high defect densities |
| 1 | Osei Poku, Ronald D. Blanton |
Delay defect diagnosis using segment network faults. |
ITC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Tao Jiang, R. D. (Shawn) Blanton |
Inductive fault analysis of surface-micromachined MEMS. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeffrey E. Nelson, Thomas Zanon, Jason G. Brown, Osei Poku, R. D. (Shawn) Blanton, Wojciech Maly, Brady Benware, Chris Schuermyer |
Extracting Defect Density and Size Distributions from Product ICs. |
IEEE Design & Test of Computers |
2006 |
DBLP DOI BibTeX RDF |
size distributions, product IC, defect density |
| 1 | Jeffrey E. Nelson, Jason G. Brown, Rao Desineni, R. D. (Shawn) Blanton |
Multiple-detect ATPG based on physical neighborhoods. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
N-detect, multiple-detect, ATPG, defects, neighborhoods |
| 1 | Jason G. Brown, R. D. (Shawn) Blanton |
Exploiting Regularity for Inductive Fault Analysis. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeffrey E. Nelson, Thomas Zanon, Rao Desineni, Jason G. Brown, N. Patil, Wojciech Maly, R. D. (Shawn) Blanton |
Extraction of defect density and size distributions from wafer sort test results. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ronald D. Blanton, Kumar N. Dwarakanath, Rao Desineni |
Defect Modeling Using Fault Tuples. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sounil Biswas, Ronald D. Blanton |
Statistical Test Compaction Using Binary Decision Trees. |
IEEE Design & Test of Computers |
2006 |
DBLP DOI BibTeX RDF |
statistical test compaction, redundant tests, kept tests, go/no-go testing, heterogeneous devices, binary decision trees |
| 1 | Naresh K. Bhatti, Ronald D. Blanton |
Diagnostic Test Generation for Arbitrary Faults. |
ITC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Rao Desineni, Osei Poku, Ronald D. Blanton |
A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior. |
ITC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Rao Desineni, R. D. (Shawn) Blanton |
Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction. |
VTS |
2005 |
DBLP DOI BibTeX RDF |
test generation, Diagnosis, defects, failure analysis, yield enhancement |
| 1 | R. D. (Shawn) Blanton, Subhasish Mitra |
Testing Nanometer Digital Integration Circuits: Myths, Reality and the Road Ahead. (PDF / PS) |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi |
Specification Test Compaction for Analog Circuits and MEMS. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason G. Brown, R. D. (Shawn) Blanton |
CAEN-BIST: Testing the NanoFabric. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas J. Vogels, Thomas Zanon, Rao Desineni, R. D. (Shawn) Blanton, Wojciech Maly, Jason G. Brown, Jeffrey E. Nelson, Y. Fei, X. Huang, Padmini Gopalakrishnan, Mahim Mishra, Vyacheslav Rovner, S. Tiwary |
Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Nilmoni Deb, R. D. (Shawn) Blanton |
Multi-Modal Built-In Self-Test for Symmetric Microsystems. |
VTS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Sounil Biswas, Kumar N. Dwarakanath, R. D. (Shawn) Blanton |
Generalized Sensitization using Fault Tuples. |
VTS |
2004 |
DBLP DOI BibTeX RDF |
multiple path sensitization, hazard-free test, fault model, Fault simulation, robust test |
| 1 | Chunsheng Liu, Kumar N. Dwarakanath, Krishnendu Chakrabarty, Ronald D. Blanton |
Compact Dictionaries for Diagnosis of Unmodeled Faults in Scan-BIST. |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Wojciech Maly, Anne E. Gattiker, Thomas Zanon, Thomas J. Vogels, R. D. (Shawn) Blanton, Thomas M. Storey |
Deformations of IC Structure in Test and Yield Learning. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
yield learning, defect characterization, diagnosis, fault modeling, defects |
| 1 | Rahul Kundu, R. D. (Shawn) Blanton |
Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas J. Vogels, Wojciech Maly, R. D. (Shawn) Blanton |
Progressive Bridge Identification. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | R. D. (Shawn) Blanton, Kumar N. Dwarakanath, Anirudh B. Shah |
Analyzing the Effectiveness of Multiple-Detect Test Sets. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Rahul Kundu, R. D. (Shawn) Blanton |
ATPG for Noise-Induced Switch Failures in Domino Logic. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ronald D. Blanton, John P. Hayes |
On the properties of the input pattern fault model. |
ACM Trans. Design Autom. Electr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
fault testing, testing digital circuits, ATPG, fault models, faults, defects |
| 1 | Nilmoni Deb, R. D. (Shawn) Blanton |
Built-In Self Test of CMOS-MEMS Accelerometers. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Kumar N. Dwarakanath, R. D. (Shawn) Blanton |
Exploiting Dominance and Equivalence using Fault Tuples. |
VTS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Salvador Mir, H. Bederr, R. D. (Shawn) Blanton, Hans G. Kerkhoff, H. J. Klim |
SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow? (PDF / PS) |
VTS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Rahul Kundu, R. D. (Shawn) Blanton |
Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits. |
VTS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Keerthi Heragu, Manish Sharma, Rahul Kundu, Ronald D. Blanton |
Test vector generation for charge sharing failures in dynamic logic. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Pranab K. Nag, Anne E. Gattiker, Sichao Wei, Ronald D. Blanton, Wojciech Maly |
Modeling the Economics of Testing: A DFT Perspective. |
IEEE Design & Test of Computers |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Ronald D. Blanton, John T. Chen, Rao Desineni, Kumar N. Dwarakanath, Wojciech Maly, Thomas J. Vogels |
Fault Tuples in Diagnosis of Deep-Submicron Circuits. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
fault model and characterization, diagnosis, failure analysis |
| 1 | Keerthi Heragu, Manish Sharma, Rahul Kundu, R. D. (Shawn) Blanton |
Testing of Dynamic Logic Circuits Based on Charge Sharing. |
VTS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Ravishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi |
False Coupling Interactions in Static Timing Analysis. |
DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen |
A Buffer-Oriented Methodology for Microarchitecture Validation. |
J. Electronic Testing |
2000 |
DBLP DOI BibTeX RDF |
processor validation, superscalar microarchitecture, design validation |
| 1 | Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen |
Effectiveness of Microarchitecture Test Program Generation. |
IEEE Design & Test of Computers |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Ronald D. Blanton, John P. Hayes |
On the design of fast, easily testable ALU's. |
IEEE Trans. VLSI Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Rao Desineni, Kumar N. Dwarakanath, Ronald D. Blanton |
Universal test generation using fault tuples. |
ITC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Rahul Kundu, Ronald D. Blanton |
Identification of crosstalk switch failures in domino CMOS circuits. |
ITC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Nilmoni Deb, Ronald D. Blanton |
Analysis of failure sources in surface-micromachined MEMS. |
ITC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Kumar N. Dwarakanath, Ronald D. Blanton |
Universal fault simulation using fault tuples. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Bernard Courtois, R. D. (Shawn) Blanton |
Guest Editors' Introduction. |
IEEE Design & Test of Computers |
1999 |
DBLP BibTeX RDF |
|
| 1 | Tamal Mukherjee, Gary K. Fedder, R. D. (Shawn) Blanton |
Hierarchical Design and Test of Integrated Microsystems. |
IEEE Design & Test of Computers |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | R. D. (Shawn) Blanton |
IDDQ-Testability of Tree Circuits. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen |
Superscalar Processor Validation at the Microarchitecture Level. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Tao Jiang, Ronald D. Blanton |
Particulate failures for surface-micromachined MEMS. |
ITC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhijeet Kolpekwar, Chris S. Kellen, Ronald D. Blanton |
MEMS fault model generation using CARAMEL. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhijeet Kolpekwar, Ronald D. Blanton, David Woodilla |
Failure modes for stiction in surface-micromachined MEMS. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | R. D. (Shawn) Blanton, John P. Hayes |
Testability Properties of Divergent Trees. |
J. Electronic Testing |
1997 |
DBLP DOI BibTeX RDF |
regular circuits, interactive logic arrays, structured circuits, test generation, fault detection, fault modeling |
| 1 | Sichao Wei, Pranab K. Nag, Ronald D. Blanton, Anne E. Gattiker, Wojciech Maly |
To DFT or Not to DFT? |
ITC |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhijeet Kolpekwar, Ronald D. Blanton |
Development of a MEMS Testing Methodology. |
ITC |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Ronald D. Blanton, John P. Hayes |
The input pattern fault model and its application. |
ED&TC |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Ronald D. Blanton, John P. Hayes |
Properties of the Input Pattern Fault Model. |
ICCD |
1997 |
DBLP BibTeX RDF |
|
| 1 | R. D. (Shawn) Blanton, John P. Hayes |
Design of a fast, easily testable ALU. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
ALU, adder design, L-testable design, level-testable, carry-lookahead addition, fault diagnosis, logic testing, integrated circuit testing, automatic testing, digital arithmetic, integrated circuit design, adders, logic arrays, test patterns, area overhead, functional faults, carry logic, arithmetic-logic unit, 8 bit |
| 1 | Ronald D. Blanton, John P. Hayes |
Testability of Convergent Tree Circuits. |
IEEE Trans. Computers |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal, Ronald D. Blanton, Maurizio Damiani |
Synthesis of Self-Testing Finite State Machines from High-Level Specifications. |
ITC |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Ronald D. Blanton, John P. Hayes |
Efficient Testing of Tree Circuits. |
FTCS |
1993 |
DBLP DOI BibTeX RDF |
|
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