Search results for "Rouwaida Kanj"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Rouwaida Kanj, Rajiv V. Joshi	A novel sample reuse methodology for fast statistical simulations with applications to manufacturing variability.	ISQED	2012	DBLP DOI BibTeX RDF
1	Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif	The Impact of Statistical Leakage Models on Design Yield Estimation.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Rajiv V. Joshi, Rouwaida Kanj, V. Ramadurai	A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Rouwaida Kanj, Tong Li, Rajiv V. Joshi, Kanak Agarwal, Ali Sadigh, David Winston, Sani R. Nassif	Accelerated statistical simulation via on-demand Hermite spline interpolations.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Rajiv V. Joshi, Rouwaida Kanj, Peiyuan Wang, Hai Helen Li	Universal statistical cure for predicting memory loss.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Rajiv V. Joshi, Rouwaida Kanj, Anthony Pelella, Arthur Tuminaro, Yuen H. Chan	The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory Lane.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF
1	Jeanne Bickford, Nazmul Habib, John Goss, Robert McMahon, Rajiv V. Joshi, Rouwaida Kanj	Use of scalable Parametric Measurement Macro to improve semiconductor technology characterization and product test.	ISQED	2010	DBLP DOI BibTeX RDF
1	Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif	Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives.	ISLPED	2010	DBLP DOI BibTeX RDF	sram
1	Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj	FinFET SRAM Design.	VLSI Design	2010	DBLP DOI BibTeX RDF	variability, SRAM, FinFET, Double gate
1	Rouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, William R. Reohr, Sani R. Nassif, Kevin J. Nowka	Statistical yield analysis of silicon-on-insulator embedded DRAM.	ISQED	2009	DBLP DOI BibTeX RDF
1	Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi	The impact of BEOL lithography effects on the SRAM cell performance and yield.	ISQED	2009	DBLP DOI BibTeX RDF
1	Rouwaida Kanj, Rajiv V. Joshi, Chad Adams, James Warnock, Sani R. Nassif	An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects.	ICCAD	2009	DBLP BibTeX RDF
1	Aditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-Fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das	Yield estimation of SRAM circuits using "Virtual SRAM Fab".	ICCAD	2009	DBLP BibTeX RDF
1	Rouwaida Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif	Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield.	ISQED	2008	DBLP DOI BibTeX RDF	decoupled design, 8T, 6T, stacked devices, stability, yield, sram, double gate
1	Rouwaida Kanj, Zhuo Li, Rajiv V. Joshi, Frank Liu, Sani R. Nassif	A Root-Finding Method for Assessing SRAM Stability.	ISQED	2008	DBLP DOI BibTeX RDF	stability, memory, yield, sram, roots
1	Rouwaida Kanj, Rajiv V. Joshi, Zhou Li, Jente B. Kuang, Hung C. Ngo, Ying Zhou, Weiping Shi, Sani R. Nassif	SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif	Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs.	ISQED	2007	DBLP DOI BibTeX RDF
1	Amin Khajeh Djahromi, Ahmed M. Eltawil, Fadi J. Kurdahi, Rouwaida Kanj	Cross Layer Error Exploitation for Aggressive Voltage Scaling.	ISQED	2007	DBLP DOI BibTeX RDF
1	Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang	A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies.	ISLPED	2007	DBLP DOI BibTeX RDF	booster circuit, low power, yield, SRAM
1	Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park, Rouwaida Kanj, Sani R. Nassif	System-Level SRAM Yield Enhancement.	ISQED	2006	DBLP DOI BibTeX RDF
1	Praveen Elakkumanan, Jente B. Kuang, Kevin J. Nowka, Ramalingam Sridhar, Rouwaida Kanj, Sani R. Nassif	SRAM Local Bit Line Access Failure Analyses.	ISQED	2006	DBLP DOI BibTeX RDF
1	Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif	Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events.	DAC	2006	DBLP DOI BibTeX RDF	statistical performance analysis, SRAM, yield prediction
1	Rouwaida Kanj, Elyse Rosenbaum	Critical evaluation of SOI design guidelines.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Rouwaida Kanj, Timothy Lehner, Bhavna Agrawal, Elyse Rosenbaum	Noise characterization of static CMOS gates.	DAC	2004	DBLP DOI BibTeX RDF	circuit-equivalent model, simulation, mathematical model, sensitivity, noise analysis, cell model
1	Rouwaida Kanj, Elyse Rosenbaum	A critical look at design guidelines for SOI logic gates.	ISCAS	2002	DBLP DOI BibTeX RDF

Publications of "Rouwaida Kanj" ( http://dblp.L3S.de/Authors/Rouwaida_Kanj )