Search results for "Rubin A. Parekhji"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi	Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test.	J. Low Power Electronics	2011	DBLP BibTeX RDF
1	Rajesh Mittal, Lakshmanan Balasubramanian, Adesh Sontakke, Harikrishna Parthasarathy, Prakash Narayanan, Puneet Sabbarwal, Rubin A. Parekhji	DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management.	ITC	2011	DBLP DOI BibTeX RDF
1	Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji	Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Srinivasulu Alampally, R. T. Venkatesh, P. Shanmugasundaram, Rubin A. Parekhji, V. D. Agrawal	An efficient test data reduction technique through dynamic pattern mixing across multiple fault models.	VTS	2011	DBLP DOI BibTeX RDF
1	Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi	Multi-CoDec Configurations for Low Power and High Quality Scan Test.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	V. Prasanth, Virendra Singh, Rubin A. Parekhji	Reduced overhead soft error mitigation using error control coding techniques.	IOLTS	2011	DBLP DOI BibTeX RDF
1	M. Kiran Kumar Reddy, Bharadwaj S. Amrutur, Rubin A. Parekhji	False Error Vulnerability Study of On-line Soft Error Detection Mechanisms.	J. Electronic Testing	2010	DBLP BibTeX RDF
1	Amit Sabne, Rajesh Tiwari, Abhijeet Shrivastava, Srivaths Ravi, Rubin A. Parekhji	A generic low power scan chain wrapper for designs using scan compression.	VTS	2010	DBLP DOI BibTeX RDF
1	Rubin A. Parekhji	Innovative practices session 1C: Innovative practices in RF test.	VTS	2010	DBLP DOI BibTeX RDF
1	Rajesh Mittal, Adesh Sontakke, Rubin A. Parekhji	Test time reduction using parallel RF test techniques.	VTS	2010	DBLP DOI BibTeX RDF
1	V. Prasanth, Virendra Singh, Rubin A. Parekhji	Robust detection of soft errors using delayed capture methodology.	IOLTS	2010	DBLP DOI BibTeX RDF
1	Hongxia Fang, Krishnendu Chakrabarty, Rubin A. Parekhji	Bit-Operation-Based Seed Augmentation for LFSR Reseeding with High Defect Coverage.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Amit Dutta, Malav Shah, G. Swathi, Rubin A. Parekhji	Design techniques and tradeoffs in implementing non-destructive field test using logic BIST self-test.	IOLTS	2009	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Rubin A. Parekhji, Jayashree Saxena	Low Power Test for Nanometer System-on-Chips (SoCs).	J. Low Power Electronics	2008	DBLP DOI BibTeX RDF
1	Amit Dutta, Srinivasulu Alampally, V. Prasanth, Rubin A. Parekhji	DFT Implementationis for Striking the Right Balance between Test Cost and Test Quality for Automotive SOCs.	ITC	2008	DBLP DOI BibTeX RDF
1	Rajesh Tiwari, Abhijeet Shrivastava, Mahit Warhadpande, Srivaths Ravi, Rubin A. Parekhji	A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips.	VTS	2008	DBLP DOI BibTeX RDF	Tester, ATPG, Estimation, ATE, Test Time, Test Data Volume
1	M. Kiran Kumar Reddy, Bharadwaj S. Amrutur, Rubin A. Parekhji	False Error Study of On-line Soft Error Detection Mechanisms.	IOLTS	2008	DBLP DOI BibTeX RDF
1	Sudhakar Surendran, Rubin A. Parekhji, R. Govindarajan	A systematic approach to synthesis of verification test-suites for modular SoC designs.	SoCC	2008	DBLP DOI BibTeX RDF
1	Subir K. Roy, Rubin A. Parekhji	Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Sandeep Jain, Jais Abraham, Srinivas Kumar Vooka, Sumant Kale, Amit Dutta, Rubin A. Parekhji	Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Satish Yada, Bharadwaj S. Amrutur, Rubin A. Parekhji	Modified Stability Checking for On-line Error Detection.	VLSI Design	2007	DBLP DOI BibTeX RDF	crosstalk faults and transient faults, SEU testing, modified stability checking, delay faults, self-checking circuits, Concurrent testing, on-line error detection
1	Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji	Methodology for low power test pattern generation using activity threshold control logic.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Sanjay K. Thakur, Rubin A. Parekhji, Arun N. Chandorkar	On-chip Test and Repair of Memories for Static and Dynamic Faults.	ITC	2006	DBLP DOI BibTeX RDF
1	Rubin A. Parekhji	Session Abstract.	VTS	2006	DBLP DOI BibTeX RDF
1	Rubin A. Parekhji	DFT for Low Cost SOC Test.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Sameer Goel, Rubin A. Parekhji	Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	delay fault simulation, N-detect coverage metrics, Delay fault test, test optimizations
1	Carol Stolicny, Tapio Koivukangas, Rubin A. Parekhji, Ian G. Harris, Rob Aitken	ITC 2003 panels: Part 1.	IEEE Design & Test of Computers	2004	DBLP BibTeX RDF
1	K. Nikila, Rubin A. Parekhji	DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI's TNETD7300 ADSL Modem Device.	ITC	2004	DBLP DOI BibTeX RDF
1	Ambar A. Gadkari, S. Ramesh, Rubin A. Parekhji	CESC: a visual formalism for specification and verification of SoCs.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	verification, specification, visual languages, system-level design
1	Rajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji, Arun N. Chandorkar	Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories.	VLSI Design	2004	DBLP DOI BibTeX RDF	Built-in self-test for memories, neighbourhood pattern sensitive faults, programmable BIST
1	Rubin A. Parekhji	Panel Synopsis - How (In)Adequate is One Time Testing?	ITC	2003	DBLP DOI BibTeX RDF
1	Rubin A. Parekhji	Testing Embedded Cores and SOCs-DFT, ATPG and BIST Solutions.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji	Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon.	VLSI Design	2002	DBLP DOI BibTeX RDF
1	Jais Abraham, Narayan Prasad, Srinivasa Chakravarthy B. S., Ameet Bagwe, Rubin A. Parekhji	A framework to evaluate test tradeoffs in embedded core based systems-case study on TI's TMS320C27xx.	ITC	2000	DBLP DOI BibTeX RDF
1	Ameet Bagwe, Rubin A. Parekhji	Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	fault coverage enhancement, embedded core based systems, test constraints, Texas Instruments TMS320C27xx, memory wrapper logic, fault diagnosis, logic testing, integrated circuit testing, application specific integrated circuits, functional testing, digital signal processing chips, fault analysis
1	Rubin A. Parekhji	Test Techniques and Trade-offs for Embedded Cores and Systems.	VLSI Design	2000	DBLP BibTeX RDF
1	Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar	Monitoring machine based synthesis technique for concurrent error detection in finite state machines.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	monitoring machines, finite state machine synthesis, concurrent error detection
1	Michael Nicolaidis, Rubin A. Parekhji, M. Boudjit	E-Groups: A New Technique for Fast Backward Propagation in System Level Test Generation.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
1	Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar	Concurrent Error Detection Using Monitoring Machines.	IEEE Design & Test of Computers	1995	DBLP DOI BibTeX RDF
1	B. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh	A new methodology for the design of low-cost fail safe circuits and networks.	VLSI Design	1995	DBLP DOI BibTeX RDF	low-cost fail safe circuits, safety critical electronic systems, input-output encoding problems, output encoding technique, low-cost design, systematic framework, graph theory, design methodology, encoding, combinational circuits, combinational circuits, graph embedding, graceful degradation, logic partitioning
1	Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar	State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits.	VLSI Design	1993	DBLP BibTeX RDF
1	Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar	A Methodology for Designing Optimal Self-Checking Sequential Circuits.	ITC	1991	DBLP DOI BibTeX RDF
1	Rubin A. Parekhji, N. K. Nanda	Design methodology and microdiagnostics development for a self-checking microprocessor.	MICRO	1989	DBLP DOI BibTeX RDF	Zilog Z8000

Publications of "Rubin A. Parekhji" ( http://dblp.L3S.de/Authors/Rubin_A._Parekhji )