Search results for "Runahead Execution"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Polychronis Xekalakis, Nikolas Ioannou, Marcelo Cintra	Combining thread level speculation helper threads and runahead execution.	ICS	2009	DBLP DOI BibTeX RDF	multi-cores, thread-level speculation, helper threads, runahead execution
3	Onur Mutlu, Hyesoon Kim, Yale N. Patt	Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance.	IEEE Micro	2006	DBLP DOI BibTeX RDF	memory latency tolerance, processors, Runahead execution
3	Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt	An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	processor performance modeling, speculative execution, runahead execution, Single data stream architectures
2	Martin Karlsson, Erik Hagersten	Conserving Memory Bandwidth in Chip Multiprocessors with Runahead Execution.	IPDPS	2007	DBLP DOI BibTeX RDF
2	Onur Mutlu, Hyesoon Kim, Yale N. Patt	Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	value prediction, memory-level parallelism, runahead execution, Single data stream architectures
2	Onur Mutlu, Hyesoon Kim, Jared Stark, Yale N. Patt	On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor.	Computer Architecture Letters	2005	DBLP DOI BibTeX RDF
2	Onur Mutlu, Hyesoon Kim, Yale N. Patt	Techniques for Efficient Processing in Runahead Execution Engines.	ISCA	2005	DBLP DOI BibTeX RDF
2	Onur Mutlu, Hyesoon Kim, Yale N. Patt	Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns.	MICRO	2005	DBLP DOI BibTeX RDF
2	Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt	Runahead Execution: An Effective Alternative to Large Instruction Windows.	IEEE Micro	2003	DBLP DOI BibTeX RDF
2	Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt	Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors.	HPCA	2003	DBLP DOI BibTeX RDF
1	Kaveh Aasaraai, Andreas Moshovos	NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution.	Int. J. Reconfig. Comp.	2012	DBLP DOI BibTeX RDF
1	Walter Yuan-Hwa Li, Chin-Ling Huang, Chung-Ping Chung	Tolerating Load Miss-Latency by Extending Effective Instruction Window with Low Complexity.	ICPP	2011	DBLP DOI BibTeX RDF	Execute Ahead, Hardware Speculation, Instruction-Level Parallelism, Processor Architecture, Memory-Level Parallelism, Runahead Execution
1	Harold W. Cain, Priya Nagpurkar	Runahead execution vs. conventional data prefetching in the IBM POWER6 microprocessor.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Kenzo Van Craeynest, Stijn Eyerman, Lieven Eeckhout	MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Peng Zhou, Soner Önder	Improving single-thread performance with fine-grain state maintenance.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	processor state, runahead, simultaneous multi-threading, checkpoint, recovery
1	Ronald D. Barnes, John W. Sias, Erik M. Nystrom, Sanjay J. Patel, Jose (Nacho) Navarro, Wen-mei W. Hwu	Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	cache-miss tolerance, prefetching, out-of-order execution, Runahead execution
1	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero	Kilo-instruction processors, runahead and prefetching.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	runahead, prefetching, speculative execution, memory wall, Kilo-instruction processors
1	Zhen Yang, Xudong Shi, Feiqi Su, Jih-Kwon Peir	Overlapping dependent loads with addressless preload.	PACT	2006	DBLP DOI BibTeX RDF	instruction and issue window, pointer-chasing loads, data prefetching, memory-level parallelism
1	Luis Ceze, Karin Strauss, James Tuck, Josep Torrellas, Jose Renau	CAVA: Using checkpoint-assisted value prediction to hide L2 misses.	TACO	2006	DBLP DOI BibTeX RDF	checkpointed processor architectures, multiprocessor, memory hierarchies, Value prediction
1	Ilya Ganusov, Martin Burtscher	Future execution: A prefetching mechanism that uses multiple cores to speed up single threads.	TACO	2006	DBLP DOI BibTeX RDF	Future execution, chip multiprocessors, prefetching, memory wall
1	Ilya Ganusov, Martin Burtscher	On the importance of optimizing the configuration of stream prefetchers.	Memory System Performance	2005	DBLP DOI BibTeX RDF	hardware prefetching, stream prefetcher, runahead execution
1	Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt	Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References.	International Journal of Parallel Programming	2005	DBLP DOI BibTeX RDF	cache filtering, speculative memory references, Caches, runahead execution, cache pollution
1	Ilya Ganusov, Martin Burtscher	Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors.	IEEE PACT	2005	DBLP DOI BibTeX RDF
1	Matthew Curtis-Maury, Tanping Wang	Integrating Multiple Forms of Multithreaded Execution on multi-SMT Systems: A Study with Scientific Applications.	QEST	2005	DBLP DOI BibTeX RDF
1	Sorin Iacobovici, Lawrence Spracklen, Sudarshan Kadambi, Yuan Chou, Santosh G. Abraham	Effective stream-based and execution-based data prefetching.	ICS	2004	DBLP DOI BibTeX RDF	hardware prefetcher, multiple strides, stream prefetching
1	Yuan Chou, Brian Fahs, Santosh G. Abraham	Microarchitecture Optimizations for Exploiting Memory-Level Parallelism.	ISCA	2004	DBLP DOI BibTeX RDF