| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Jia Zhao, Russell Tessier, Wayne Burleson |
Distributed sensor data processing for many-cores.  |
ACM Great Lakes Symposium on VLSI  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Dong Yin, Deepak Unnikrishnan, Yong Liao, Lixin Gao, Russell Tessier |
Customizing virtual networks with partial FPGA reconfiguration. |
Computer Communication Review |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tilman Wolf, Russell Tessier, Gayatri Prabhu |
Securing the data path of next-generation router systems. |
Computer Communications |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jia Zhao, Sailaja Madduri, Ramakrishna Vadlamani, Wayne Burleson, Russell Tessier |
A Dedicated Monitoring Infrastructure for Multicore Processors. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Emmanuel Seguin, Russell Tessier, Eric Knapp, Robert W. Jackson |
A Dynamically-Reconfigurable Phased Array Radar Processing System. |
FPL |
2011 |
DBLP DOI BibTeX RDF |
dynamic reconfiguration, beamforming, radar |
| 1 | Jérémie Crenne, Pascal Cotret, Guy Gogniat, Russell Tessier, Jean-Philippe Diguet |
Efficient key-dependent message authentication in reconfigurable hardware. |
FPT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Russell Tessier (eds.) |
2011 International Conference on Field-Programmable Technology, FPT 2011, New Delhi, India, December 12-14, 2011 |
FPT |
2011 |
DBLP BibTeX RDF |
|
| 1 | Deepak Unnikrishnan, Justin Lu, Lixin Gao, Russell Tessier |
ReClick - A Modular Dataplane Design Framework for FPGA-Based Network Virtualization. |
ANCS |
2011 |
DBLP DOI BibTeX RDF |
Click modular router, FPGA, Programming models, Network Virtualization, NetFPGA |
| 1 | Ben Bovee, Mohammad Nekoui, Hossein Pishro-Nik, Russell Tessier |
Evaluation of the Universal Geocast Scheme for VANETs. |
VTC Fall |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Russell Tessier, Salma Mirza, J. Blair Perot |
Reconfigurable Sparse Matrix-Vector Multiplication on FPGAs. |
ERSA |
2010 |
DBLP BibTeX RDF |
|
| 1 | Jia Zhao, Basab Datta, Wayne P. Burleson, Russell Tessier |
Thermal-aware voltage droop compensation for multi-core architectures. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
monitor network-on-chip, thermal monitor, voltage emergency |
| 1 | Ron Sass, Russell Tessier (eds.) |
18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2010, Charlotte, North Carolina, USA, 2-4 May 2010 |
FCCM |
2010 |
DBLP BibTeX RDF |
|
| 1 | Deepak Unnikrishnan, Ramakrishna Vadlamani, Yong Liao, Abhishek Dwaraki, Jérémie Crenne, Lixin Gao, Russell Tessier |
Scalable network virtualization using FPGAs. |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
FPGA, virtual networks |
| 1 | Ramakrishna Vadlamani, Jia Zhao, Wayne P. Burleson, Russell Tessier |
Multicore soft error rate stabilization using adaptive dual modular redundancy. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Eduardo Wanderley Netto, Russell Tessier, Wayne P. Burleson |
A security approach for off-chip memory in embedded microprocessor systems. |
Microprocessors and Microsystems - Embedded Hardware Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Weifeng Xu, Russell Tessier |
Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors. |
TACO |
2009 |
DBLP DOI BibTeX RDF |
Very Long Instruction Word (VLIW) processor, instruction level parallelism, Register pressure |
| 1 | Kevin Andryc, Russell Tessier, Patrick Kelly |
An Interactive Approach to Timing Accurate PCI-X Simulation. |
IEEE International Workshop on Rapid System Prototyping |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Deepak Unnikrishnan, Jia Zhao, Russell Tessier |
Application Specific Customization and Scalability of Soft Multiprocessors. |
FCCM |
2009 |
DBLP DOI BibTeX RDF |
soft multiprocessor, application specific customization, FPGA, architectural evaluation, automatic compilation |
| 1 | Tilman Wolf, Russell Tessier |
Design of a Secure Router System for Next-Generation Networks. |
NSS |
2009 |
DBLP DOI BibTeX RDF |
processor monitor, network security, embedded processor, router design |
| 1 | Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger |
CMOS vs Nano: comrades or rivals? |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
fpga, nanotechnology |
| 1 | Sailaja Madduri, Ramakrishna Vadlamani, Wayne Burleson, Russell Tessier |
A monitor interconnect and support subsystem for multicore processors. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Ian Kuon, Russell Tessier, Jonathan Rose |
FPGA Architecture: Survey and Challenges. |
Foundations and Trends in Electronic Design Automation |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Russell Tessier, Vaughn Betz, David Neto, Aaron Egier, Thiagaraja Gopalsamy |
Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Russell Tessier, Wayne Burleson |
High-efficiency protection solution for off-chip memory in embedded systems. |
ERSA |
2007 |
DBLP BibTeX RDF |
|
| 1 | Thomas Eisenbarth, Tim Güneysu, Christof Paar, Ahmad-Reza Sadeghi, Marko Wolf, Russell Tessier |
Establishing Chain of Trust in Reconfigurable Hardware. |
FCCM |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kevin Oo Tinmaung, David Howland, Russell Tessier |
Power-aware FPGA logic synthesis using binary decision diagrams. |
FPGA |
2007 |
DBLP DOI BibTeX RDF |
FPGA, binary decision diagram, dynamic power |
| 1 | Romain Vaslin, Guy Gogniat, Eduardo Wanderley Netto, Russell Tessier, Wayne P. Burleson |
Low latency Solution for Confidentiality and Integrity Checking in Embedded Systems with Off-Chip Memory. |
ReCoSoC |
2007 |
DBLP BibTeX RDF |
|
| 1 | Weifeng Xu, Russell Tessier |
Tetris: a new register pressure control technique for VLIW processors. |
LCTES |
2007 |
DBLP DOI BibTeX RDF |
register pressure control, very long instruction word (VLIW) processor, instruction level parallelism |
| 1 | Miriam Leeser, Scott Hauck, Russell Tessier |
Field-Programmable Gate Arrays in Embedded Systems. |
EURASIP J. Emb. Sys. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Premachandran R. Menon, Weifeng Xu, Russell Tessier |
Design-specific path delay testing in lookup-table-based FPGAs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Lilian Atieno, Jonathan Allen, Dennis Goeckel, Russell Tessier |
An adaptive Reed-Solomon errors-and-erasures decoder. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
FPGA, power reduction, Reed-Solomon |
| 1 | Russell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy |
Power-aware RAM mapping for FPGA embedded memory blocks. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
embedded memory block, FPGA, dynamic power |
| 1 | Russell Tessier, David Jasinski, Atul Maheshwari, Aiyappan Natarajan, Weifeng Xu, Wayne P. Burleson |
An energy-aware active smart card. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Russell Tessier, Sriram Swaminathan, Ramaswamy Ramaswamy, Dennis Goeckel, Wayne P. Burleson |
A reconfigurable, power-efficient adaptive Viterbi decoder. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jian Liang, Andrew Laffely, S. Srinivasan, Russell Tessier |
An architecture and compiler for scalable on-chip communication. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Atul Maheshwari, Wayne Burleson, Russell Tessier |
Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP BibTeX RDF |
|
| 1 | Prashant Jain, Andrew Laffely, Wayne Burleson, Russell Tessier, Dennis Goeckel |
Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations. |
VLSI Signal Processing |
2004 |
DBLP DOI BibTeX RDF |
VLSI, motion estimation, digital signal processing, MPEG, power-aware |
| 1 | Roger Woods, Russell Tessier |
Guest Editorial: Field Programmable Logic. |
VLSI Signal Processing |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Jian Liang, Russell Tessier, Dennis Goeckel |
A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder. |
FCCM |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Russell Tessier, Herman Schmit (eds.) |
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004 |
FPGA |
2004 |
DBLP BibTeX RDF |
|
| 1 | Srini Krishnamoorthy, Russell Tessier |
Technology mapping algorithms for hybrid FPGAs containing lookup tables and PLAs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiyappan Natarajan, David Jasinski, Wayne Burleson, Russell Tessier |
A hybrid adiabatic content addressable memory for ultra low-power applications. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
adiabatic switching, ultra-low power, energy recovery |
| 1 | Andrew Laffely, Jian Liang, Russell Tessier, Wayne Burleson |
Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores. |
ICIP |
2003 |
DBLP BibTeX RDF |
|
| 1 | Weifeng Xu, Ramshankar Ramanarayanan, Russell Tessier |
Adaptive Fault Recovery for Networked Reconfigurable Systems. |
FCCM |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jian Liang, Russell Tessier, Oskar Mencer |
Floating Point Unit Generation and Evaluation for FPGAs. |
FCCM |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Navin Vemuri, Priyank Kalla, Russell Tessier |
BDD-based logic synthesis for LUT-based FPGAs. |
ACM Trans. Design Autom. Electr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
FPGA, decomposition, logic synthesis, BDD |
| 1 | Russell Tessier |
Fast placement approaches for FPGAs. |
ACM Trans. Design Autom. Electr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
field-programmable gate arrays, synthesis, layout, Computer-aided design of VLSI |
| 1 | Murali Kudlugi, Russell Tessier |
Static scheduling of multidomain circuits for fast functional verification. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Ian G. Harris, Russell Tessier |
Testing and diagnosis of interconnect faults in cluster-based FPGA architectures. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Atul Maheshwari, Wayne Burleson, Russell Tessier |
Trading off Reliability and Power-Consumption in Ultra-low Power Systems. (PDF / PS) |
ISQED |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Ramaswamy Ramaswamy, Russell Tessier |
The Integration of SystemC and Hardware-Assisted Verification. |
FPL |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Sriram Swaminathan, Russell Tessier, Dennis Goeckel, Wayne Burleson |
A dynamically reconfigurable adaptive viterbi decoder. |
FPGA |
2002 |
DBLP DOI BibTeX RDF |
field-programmable-gate-arrays (FPGAs), high-level synthesis, data reorganization |
| 1 | Russell Tessier, Wayne Burleson |
Reconfigurable Computing for Digital Signal Processing: A Survey. |
VLSI Signal Processing |
2001 |
DBLP DOI BibTeX RDF |
FPGA, survey, signal processing, reconfigurable computing |
| 1 | Ian G. Harris, Premachandran R. Menon, Russell Tessier |
BIST-based delay path testing in FPGA architectures. |
ITC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Murali Kudlugi, Charles Selvidge, Russell Tessier |
Static Scheduling of Multiple Asynchronous Domains For Functional Verification. |
DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Murali Kudlugi, Charles Selvidge, Russell Tessier |
Static Scheduling of Multi-Domain Memories For Functional Verification. |
ICCAD |
2001 |
DBLP BibTeX RDF |
|
| 1 | Russell Tessier, Heather Giza |
Balancing Logic Utilization and Area Efficiency in FPGAs. |
FPL |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Srini Krishnamoorthy, Sriram Swaminathan, Russell Tessier |
Area-Optimized Technology Mapping for Hybrid FPGAs. |
FPL |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Jian Liang, Sriram Swaminathan, Russell Tessier |
aSOC: A Scalable, Single-Chip Communications Architecture. |
IEEE PACT |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Ian G. Harris, Russell Tessier |
Interconnect testing in cluster-based FPGA architectures. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
field-programmable gate arrray, interconnect testing, hierarchical test |
| 1 | Vijay Lakamraju, Russell Tessier |
Tolerating operational faults in cluster-based FPGAs. |
FPGA |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Ian G. Harris, Russell Tessier |
Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures. |
ICCAD |
2000 |
DBLP BibTeX RDF |
|
| 1 | Russell Tessier |
Incremental Compilation for Logic Emulation. (PDF / PS) |
IEEE International Workshop on Rapid System Prototyping |
1999 |
DBLP DOI BibTeX RDF |
virtual wire, scheduling, partitioning, incremental, logic emulation |
| 1 | Russell Tessier |
Frontier: A Fast Placement System for FPGAs. |
VLSI |
1999 |
DBLP BibTeX RDF |
|
| 1 | Jonathan Babb, Russell Tessier, Matthew Dahl, Silvina Hanono, David M. Hoki, Anant Agarwal |
Logic emulation with virtual wires. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Steve Ward, Karim Abdalla, Rajeev Dujari, Michael Fetterman, Frank Honoré, Ricardo Jenez, Philippe Laffont, Kenneth Mackenzie, Chris Metcalf, Milan Minsky, John Nguyen, John Pezaris, Gill A. Pratt, Russell Tessier |
The NuMesh: A Modular, Scalable Communications Substrate. |
International Conference on Supercomputing |
1993 |
DBLP DOI BibTeX RDF |
|
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