Search results for "SASP"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Ganesh S. Dasika, Kevin Fan, Scott A. Mahlke	Power-efficient medical image processing using PUMA.	SASP	2009	DBLP DOI BibTeX RDF
1	Wei Han, Ying Yi, Xin Zhao, Mark Muir, Tughrul Arslan, Ahmet T. Erdogan	Heterogeneous multi-core architectures with dynamically reconfigurable processors for wireless communication.	SASP	2009	DBLP DOI BibTeX RDF
1	Hyunchul Park, Yongjun Park, Scott A. Mahlke	A dataflow-centric approach to design low power control paths in CGRAs.	SASP	2009	DBLP DOI BibTeX RDF
1	Bo Zhou, Xiaobo Sharon Hu, Danny Z. Chen, Cedric X. Yu	A multi-FPGA accelerator for radiation dose calculation in cancer treatment.	SASP	2009	DBLP DOI BibTeX RDF
1	Jehangir Khan, Smaïl Niar, Mazen A. R. Saghir, Yassin Elhillali, Atika Rivenq	Driver assistance system design and its optimization for FPGA based MPSoC.	SASP	2009	DBLP DOI BibTeX RDF
1	Ajay K. Verma, Yi Zhu, Philip Brisk, Paolo Ienne	Arithmetic optimization for custom instruction set synthesis.	SASP	2009	DBLP DOI BibTeX RDF
1	Maryam Moazeni, Alex A. T. Bui, Majid Sarrafzadeh	A memory optimization technique for software-managed scratchpad memory in GPUs.	SASP	2009	DBLP DOI BibTeX RDF
1	Yuanrui Zhang, Mahmut T. Kandemir	A hardware-software codesign strategy for Loop intensive applications.	SASP	2009	DBLP DOI BibTeX RDF
1	Mathew Paul, Peter Petrov	Dynamic and application-driven I-cache partitioning for low-power embedded multitasking.	SASP	2009	DBLP DOI BibTeX RDF
1	Amin Ansari, Dan Zhang, Scott A. Mahlke	Parade: A versatile parallel architecture for accelerating pulse train clustering.	SASP	2009	DBLP DOI BibTeX RDF
1		Proceedings of the IEEE 7th Symposium on Application Specific Processors, SASP 2009, San Francisco, CA, USA , July 27-28, 2009	SASP	2009	DBLP BibTeX RDF
1	Shoaib Akram, Rakesh Kumar, Deming Chen	Workload adaptive shared memory multicore processors with reconfigurable interconnects.	SASP	2009	DBLP DOI BibTeX RDF
1	Nam Duong, Rakesh Kumar	Register Multimapping: A technique for reducing register bank conflicts in processors with large register files.	SASP	2009	DBLP DOI BibTeX RDF
1	Giovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria	A design space exploration methodology supporting run-time resource management for multi-processor Systems-on-chip.	SASP	2009	DBLP DOI BibTeX RDF
1	Marcela Zuluaga, Theo Kluter, Philip Brisk, Nigel P. Topham, Paolo Ienne	Introducing control-flow inclusion to support pipelining in custom instruction set extensions.	SASP	2009	DBLP DOI BibTeX RDF
1	Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev	A reconfigurable beamformer for audio applications.	SASP	2009	DBLP DOI BibTeX RDF
1	Junguk Cho, Bridget Benson, Ryan Kastner	Hardware acceleration of multi-view face detection.	SASP	2009	DBLP DOI BibTeX RDF
1	Cheng Ling, Khaled Benkrid, Tsuyoshi Hamada	A parameterisable and scalable Smith-Waterman algorithm implementation on CUDA-compatible GPUs.	SASP	2009	DBLP DOI BibTeX RDF
1	Jonghee M. Youn, Minwook Ahn, Daeho Kim, Jonghee W. Yoon, Yunheung Paek, Sechul Shin, Hochang Chae, Jeonghun Cho	A new addressing mode for the encoding space problem on embedded processors.	SASP	2009	DBLP DOI BibTeX RDF
1	Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu	FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs.	SASP	2009	DBLP DOI BibTeX RDF
1	Enric Musoll	Energy and thermal tradeoffs in hardware-based load balancing for clustered multi-core architectures implementing power gating.	SASP	2008	DBLP DOI BibTeX RDF
1	Alexandros Papakonstantinou, Deming Chen, Wen-mei W. Hwu	Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor.	SASP	2008	DBLP DOI BibTeX RDF
1	Ali Irturk, Bridget Benson, Shahnam Mirzaei, Ryan Kastner	An FPGA Design Space Exploration Tool for Matrix Inversion Architectures.	SASP	2008	DBLP DOI BibTeX RDF
1	Josef B. Spjut, Solomon Boulos, Daniel Kopta, Erik Brunvand, Spencer Kellis	TRaX: A Multi-Threaded Architecture for Real-Time Ray Tracing.	SASP	2008	DBLP DOI BibTeX RDF
1	Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria	An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints.	SASP	2008	DBLP DOI BibTeX RDF
1	Sacha Loitz, Markus Wedler, Christian Brehm, Timo Vogt, Norbert Wehn, Wolfgang Kunz	Proving Functional Correctness of Weakly Programmable IPs - A Case Study with Formal Property Checking.	SASP	2008	DBLP DOI BibTeX RDF
1	Xingdong Dai, Meghanad D. Wagh	An MDCT Hardware Accelerator for MP3 Audio.	SASP	2008	DBLP DOI BibTeX RDF
1	Jelena Trajkovic, Daniel D. Gajski	Custom Processor Core Construction from C Code.	SASP	2008	DBLP DOI BibTeX RDF
1	Hai Lin 0004, Guangyu Sun, Yunsi Fei, Yuan Xie, Anand Sivasubramaniam	Thermal-aware Design Considerations for Application-Specific Instruction Set Processor.	SASP	2008	DBLP DOI BibTeX RDF
1	Kenshu Seto, Masahiro Fujita	Custom Instruction Generation with High-Level Synthesis.	SASP	2008	DBLP DOI BibTeX RDF
1	Carlos Morra, João M. P. Cardoso, João Bispo, Jürgen Becker	Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures.	SASP	2008	DBLP DOI BibTeX RDF
1		Proceedings of the IEEE Symposium on Application Specific Processors, SASP 2008, held in conjunction with the DAC 2008, June 8-9, 2008, Anaheim, California, USA	SASP	2008	DBLP BibTeX RDF
1	Kwangyoon Lee, Alex Orailoglu	Application Specific Low Latency Instruction Cache for NAND Flash Memory Based Embedded Systems.	SASP	2008	DBLP DOI BibTeX RDF
1	Marcela Zuluaga, Nigel P. Topham	Resource Sharing in Custom Instruction Set Extensions.	SASP	2008	DBLP DOI BibTeX RDF
1	Bharat Sukhwani, Alessandro Forin, Richard Neil Pittman	Extensible On-Chip Peripherals.	SASP	2008	DBLP DOI BibTeX RDF
1	Po-Kuan Huang, Matin Hashemi, Soheil Ghiasi	System-Level Performance Estimation for Application-Specific MPSoC Interconnect Synthesis.	SASP	2008	DBLP DOI BibTeX RDF
1	Shuai Che, Jie Li, Jeremy W. Sheaffer, Kevin Skadron, John Lach	Accelerating Compute-Intensive Applications with GPUs and FPGAs.	SASP	2008	DBLP DOI BibTeX RDF
1	Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi	Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays.	SASP	2008	DBLP DOI BibTeX RDF
1	Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato	AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications.	SASP	2008	DBLP DOI BibTeX RDF
1	Wei Han, Ying Yi, Mark Muir, Ioannis Nousias, Tughrul Arslan, Ahmet T. Edorgan	Multi-core Architectures with Dynamically Reconfigurable Array Processors for the WiMAX Physical Layer.	SASP	2008	DBLP DOI BibTeX RDF

Publications at "SASP"( http://dblp.L3S.de/Venues/SASP )