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Results
Found 21 publication records. Showing 21 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 2 | Sachoun Park, Gihwon Kwon |
SAT based Verification Tool for Labeled Transition System.  |
SERA  |
2007 |
DBLP DOI BibTeX RDF |
Formal Verification, Labeled Transition System, Bounded Model checking, Linear Temporal Logic |
| 2 | Wenhui Zhang |
SAT-Based Verification of LTL Formulas.  |
FMICS/PDMC  |
2006 |
DBLP DOI BibTeX RDF |
|
| 2 | Aarti Gupta, Malay K. Ganai, Chao Wang |
SAT-Based Verification Methods and Applications in Hardware Verification.  |
SFM  |
2006 |
DBLP DOI BibTeX RDF |
|
| 2 | Shougo Ogata, Tatsuhiro Tsuchiya, Tohru Kikuno |
SAT-Based Verification of Safe Petri Nets.  |
ATVA  |
2004 |
DBLP DOI BibTeX RDF |
Petri nets, SAT, Bounded model checking |
| 1 | S. Kemper |
SAT-based verification for timed component connectors.  |
Sci. Comput. Program.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mathias Soeken, Robert Wille, Rolf Drechsler |
Encoding OCL Data Types for SAT-Based Verification of UML/OCL Models.  |
TAP  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefan Schwoon, César Rodríguez |
Construction and SAT-Based Verification of Contextual Unfoldings.  |
DCFS  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Padmalochan Bera, Soumya Maity, Soumya Kanti Ghosh, Pallab Dasgupta |
A SAT Based Verification Framework for Wireless LAN Security Policy Management Supported by STRBAC Model.  |
CNSA  |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephanie Kemper |
SAT-based Verification for Timed Component Connectors.  |
Electr. Notes Theor. Comput. Sci.  |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Wenhui Zhang |
Bounded Semantics of CTL and SAT-Based Verification.  |
ICFEM  |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Padmalochan Bera, Soumya Kanti Ghosh, Pallab Dasgupta |
Fault Analysis of Security Policy Implementations in Enterprise Networks.  |
NetCoM  |
2009 |
DBLP DOI BibTeX RDF |
Access Control List(ACL), SAT based verification, Network Security, LAN |
| 1 | Marc Herbstritt |
SAT-based verification: from core algorithms to novel application domains.  |
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2008 |
RDF |
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| 1 | Jen-Chieh Ou, Daniel G. Saab, Qiang Qiang, Jacob A. Abraham |
Reducing verification overhead with RTL slicing.  |
ACM Great Lakes Symposium on VLSI  |
2007 |
DBLP DOI BibTeX RDF |
verification, test, CAD |
| 1 | Miroslaw Kurkowski, Wojciech Penczek, Andrzej Zbrzezny |
SAT-Based Verification of Security Protocols Via Translation to Networks of Automata.  |
MoChArt  |
2006 |
DBLP DOI BibTeX RDF |
model checking, authentication, security protocols |
| 1 | Weixin Wu, Michael S. Hsiao |
Mining global constraints for improving bounded sequential equivalence checking.  |
DAC  |
2006 |
DBLP DOI BibTeX RDF |
multi-node constraint, SAT, mining |
| 1 | Magdalena Kacprzak, Wojciech Penczek |
Fully Symbolic Unbounded Model Checking for Alternating-time Temporal Logic1.  |
Autonomous Agents and Multi-Agent Systems  |
2005 |
DBLP DOI BibTeX RDF |
Alternating-time Temporal Logic, unbounded model checking, SAT-based verification, multi-agent systems, symbolic model checking |
| 1 | Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Ilya Shlyakhter, Pranav Ashar |
F-Soft: Software Verification Platform.  |
CAV  |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Wojciech Penczek, Agata Pólrola |
Specification and Model Checking of Temporal Properties in Time Petri Nets and Timed Automata.  |
ICATPN  |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula |
Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines.  |
VLSI Design  |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Per Bjesse |
Industrial Model Checking Based on Satisfiability Solvers.  |
SPIN  |
2002 |
DBLP DOI BibTeX RDF |
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| 1 | Per Bjesse, Koen Claessen |
SAT-Based Verification without State Space Traversal.  |
FMCAD  |
2000 |
DBLP DOI BibTeX RDF |
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