| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Kohei Matsunobu, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri |
A discussion on calculating eigenvalues of real symmetric tridiagonal matrices on a GPU.  |
SIGARCH Computer Architecture News  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Takayuki Akamine, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano |
An implementation of out-of-order execution system for acceleration of computational fluid dynamics on FPGAs. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Thorson |
Internet nuggets. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Anindita Chakraborty, Amitabha Sinha |
Conversion of binary to single-term triple base numbers for DSP applications. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ana Balevic, Bart Kienhuis |
KPN2GPU: an approach for discovery and exploitation of fine-grain data parallelism in process networks. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tomoyuki Nagatsuka, Yoshito Sakaguchi, Takayuki Matsumura, Kenji Kise |
CoreSymphony: an efficient reconfigurable multi-core architecture. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Junying Chen, Billy Y. S. Yiu, Brandon K. Hamilton, Alfred C. H. Yu, Hayden K.-H. So |
Design space exploration of adaptive beamforming acceleration for bedside and portable medical ultrasound imaging. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Luiz Andre Barroso |
Warehouse-Scale Computing: Entering the Teenage Decade. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Miriam Leeser, Devon Yablonski, Dana Brooks, Laurie A. Smith King |
The challenges of writing portable, correct and high performance libraries for GPUs. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Antoine Trouve, Kazuaki Murakami |
Augmenting DR-ASIP flexibility through multi-mode custom instructions. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Opoku Agyeman, Ali Ahmadinia |
Power and area optimisation in heterogeneous 3D networks-on-chip architectures. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | David A. Ferrucci |
IBM's Watson/DeepQA. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kentaro Sano, Satoru Yamamoto, Yoshiaki Hatsuda |
Domain-specific programmable design of scalable streaming-array for power-efficient stencil computation. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Shinya Kubota, Minoru Watanabe |
A MEMS writer system embedded for a programmable optically reconfigurable gate array. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri, Takafumi Fujimoto |
GPU implementation and optimization of electromagnetic simulation using the FDTD method for antenna designing. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Serban Georgescu, Peter Chow |
GPU accelerated CAE using open solvers and the cloud. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Shufan Yang, T. Martin McGinnity |
A biologically plausible real-time spiking neuron simulation environment based on a multiple-FPGA platform. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Satrughna Singha, Aniruddha Ghosh, Amitabha Sinha |
A new architecture for FPGA based implementation of conversion of binary to double base number system (DBNS) using parallel search technique. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Thimmarayaswamy K, Mary M. Dsouza, G. Varaprasad |
Low power techniques for an android based phone. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Thorson |
Internet nuggets. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Dominik Meyer, Bernd Klauer |
Multicore reconfiguration platform an alternative to RAMPSoC. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hiroomi Sawada, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi |
Parallelization of the channel width search for FPGA routing. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Shoji Tanabe, Takuya Nagashima, Yoshiki Yamaguchi |
A study of an FPGA based flexible SIMD processor. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Thorson |
Internet nuggets. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Oliver Pell, Oskar Mencer |
Surviving the end of frequency scaling with reconfigurable dataflow computing. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Amila Akagic, Hideharu Amano |
High speed CRC with 64-bit generator polynomial on an FPGA. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jan Fousek, Jiri Filipovic, Matus Madzin |
Automatic fusions of CUDA-GPU kernels for parallel map. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Nathan L. Binkert, Bradford M. Beckmann, Gabriel Black, Steven K. Reinhardt, Ali G. Saidi, Arkaprava Basu, Joel Hestness, Derek Hower, Tushar Krishna, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib, Nilay Vaish, Mark D. Hill, David A. Wood |
The gem5 simulator. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ravi Kannan |
Algorithms: Recent Highlights and Challenges. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Thomasian |
Survey and analysis of disk scheduling methods. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kuen Hung Tsoi, Wayne Luk |
Power profiling and optimization for heterogeneous multi-core systems. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Haisheng Liu, Smaïl Niar, Yassin Elhillali, Atika Rivenq |
Embedded architecture with hardware accelerator for target recognition in driver assistance system. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Robin Bonamy, Daniel Chillet, Olivier Sentieys, Sebastien Bilavarn |
Parallelism Level Impact on Energy Consumption in Reconfigurable Devices. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Shinya Takamaeda-Yamazaki, Ryosuke Sasakawa, Yoshito Sakaguchi, Kenji Kise |
An FPGA-based scalable simulation accelerator for tile architectures. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Malay Das, Amitabha Sinha, Nishant Kumar Giri |
High speed residue number system (RNS) based FIR filter using distributed arithmetic (DA). |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Thomasian |
Storage research in industry and universities. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mojtaba Sabeghi, Hamid Mushtaq, Koen Bertels |
Runtime multitasking support on polymorphic platforms. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Thorson |
Internet nuggets. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kentaro Sano, Luzhou Wang, Satoru Yamamoto |
Prototype implementation of array-processor extensible over multiple FPGAs for scalable stencil computation. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk |
Efficient reconfigurable design for pricing asian options. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Claude Tadonki, Gilbert Grodidier, Olivier Pène |
An efficient CELL library for lattice quantum chromodynamics. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tadayoshi Horita, Itsuo Takanami |
An FPGA-based fast classifier with high generalization property. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Thomasian |
Why specialized disks for composite operations may be unnecessary. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Keisuke Dohi, Yuichiro Shibata, Tsuyoshi Hamada, Tomonari Masada, Kiyoshi Oguri, Duncan A. Buell |
Implementation of a programming environment with a multithread model for reconfigurable systems. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Wolfgang Matthes |
Resources instead of cores? |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hirokazu Morishita, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano |
Implementation and evaluation of an arithmetic pipeline on FLOPS-2D: multi-FPGA system. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Fuad Tabba |
Adding concurrency in python using a commercial processor's hardware transactional memory support. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ryan Taylor, Xiaoming Li |
Software-based branch predication for AMD GPUs. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Marco Aurelio Nuño-Maganda, Cesar Torres-Huitzil |
A temporal coding hardware implementation for spiking neural networks. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kuen Hung Tsoi, Anson H. T. Tse, Peter Pietzuch, Wayne Luk |
Programming framework for clusters with heterogeneous accelerators. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew Putnam, Aaron Smith, Doug Burger |
Dynamic vectorization in the E2 dynamic multicore architecture. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sebastian Banescu, Florent de Dinechin, Bogdan Pasca, Radu Tudoran |
Multipliers for floating-point double precision and beyond on FPGAs. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Shobha T, Syed Akram, G. Varaprasad |
Design and development of framework for diagnosing intermediate nodes. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Thorson |
Internet nuggets. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jong Kyung Paek, Kiyoung Choi, Jong-eun Lee |
Binary acceleration using coarse-grained reconfigurable architecture. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Thorson |
Internet nuggets. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Manideepa Mukherjee, Amitabha Sinha |
A novel architecture for conversion of binary to single digit double base numbers. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chi Chiu Tsang, Hayden Kwok-Hay So |
Dynamic power reduction of FPGA-based reconfigurable computers using precomputation. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Omid Azizi, Aqeel Mahesri, Sanjay J. Patel, Mark Horowitz |
Area-efficiency in CMP core design: co-optimization of microarchitecture and physical design. |
SIGARCH Computer Architecture News |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Thorson |
Internet nuggets. |
SIGARCH Computer Architecture News |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianwei Chen, Murali Annavaram, Michel Dubois |
SlackSim: a platform for parallel simulations of CMPs on CMPs. |
SIGARCH Computer Architecture News |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chris R. Jesshope, Mike Lankamp, Li Zhang |
The implementation of an SVP many-core processor and the evaluation of its memory architecture. |
SIGARCH Computer Architecture News |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Thorson |
Internet nuggets. |
SIGARCH Computer Architecture News |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Madhura Purnaprajna, Mario Porrmann, Ulrich Rückert |
Run-time reconfigurability in embedded multiprocessors. |
SIGARCH Computer Architecture News |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Matteo Monchiero, Jung Ho Ahn, Ayose Falcón, Daniel Ortega, Paolo Faraboschi |
How to simulate 1000 cores. |
SIGARCH Computer Architecture News |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Thorson |
Internet nuggets. |
SIGARCH Computer Architecture News |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Karan Singh, Major Bhadauria, Sally A. McKee |
Real time power estimation and thread scheduling via performance counters. |
SIGARCH Computer Architecture News |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Angel V. Nikolov |
Queuing theoretic model for a multiprocessor with private caches and shared memory. |
SIGARCH Computer Architecture News |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Thomasian |
Publications on storage and systems research. |
SIGARCH Computer Architecture News |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Enric Musoll |
Mesh-based many-core performance under process variations: a core yield perspective. |
SIGARCH Computer Architecture News |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Enric Musoll |
Leakage-saving opportunities in mesh-based massive multi-core architectures. |
SIGARCH Computer Architecture News |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jantsch |
Scalability of relaxed consistency models in NoC based multicore architectures. |
SIGARCH Computer Architecture News |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hui Zeng, Matt T. Yourst, Kanad Ghose, Dmitry Ponomarev |
MPTLsim: a cycle-accurate, full-system simulator for x86-64 multicore architectures with coherent caches. |
SIGARCH Computer Architecture News |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen |
Introduction to the special issue on the 2008 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'08). |
SIGARCH Computer Architecture News |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandeep Sharma, K. S. Kahlon, P. K. Bansal |
Reliability and path length analysis of irregular fault tolerant multistage interconnection network. |
SIGARCH Computer Architecture News |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Thorson |
Internet nuggets. |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicolas Zea, John Sartori, Rakesh Kumar |
Servo: a programming model for many-core computing. |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Wenlong Li, Yen-Kuang Chen |
Parallelization, performance analysis, and algorithm consideration of Hough transform on chip multiprocessors. |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Huan Fang, Mats Brorsson |
Scalable directory architecture for distributed shared memory chip multiprocessors. |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Thorson |
Internet nuggets. |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Karl-Filip Faxén |
Wool-A work stealing library. |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Christoph W. Kessler, Jörg Keller |
Optimized on-chip pipelining of memory-intensive computations on the cell BE. |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Shuvra S. Bhattacharyya, Gordon J. Brebner, Jörn W. Janneck, Johan Eker, Carl von Platen, Marco Mattavelli, Mickaël Raulet |
OpenDF: a dataflow toolset for reconfigurable hardware and multicore systems. |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Padma Apparao, Ravi Iyer, Don Newell |
Towards modeling & analysis of consolidated CMP servers. |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ramesh K. Karne, Alexander L. Wijesinha, George H. Ford Jr. |
Opinion: stay on course with an evolution or choose a revolution in computing. |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Javier Merino, Valentin Puente, Pablo Prieto, José-Ángel Gregorio |
SP-NUCA: a cost effective dynamic non-uniform cache architecture. |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Håkan Sundell, Philippas Tsigas |
NOBLE: non-blocking programming support via lock-free shared abstract data types. |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Li Zhao, Ravi Iyer, Mike Upton, Don Newell |
Towards hybrid last level caches for chip-multiprocessors. |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Anders Gidenstam, Marina Papatriantafilou |
LFTHREADS: a lock-free thread library. |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Parosh Aziz Abdulla, Frédéric Haziza, Mats Kindahl |
Model checking race-freeness. |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jerker Bengtsson, Bertil Svensson |
A domain-specific approach for software development on Manycore platforms. |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ravi Kiran Karanam, Arun Ravindran, Arindam Mukherjee |
A stream chip-multiprocessor for bioinformatics. |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen |
Introduction to the special issue on the 2007 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'07). |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Phuong Hoai Ha, Philippas Tsigas, Otto J. Anshus |
Non-blocking programming on multi-core graphics processors: (extended asbtract). |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Håkan Lundvall, Kristian Stavåker, Peter Fritzson, Christoph W. Kessler |
Automatic parallelization of simulation code for equation-based models with software pipelining and measurements on three platforms. |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Cederman, Philippas Tsigas |
On sorting and load balancing on GPUs. |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Divya Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger |
Multitasking workload scheduling on flexible core chip multiprocessors. |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Thorson |
Internet Nuggets. |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | David Zhang, Qiuyuan J. Li, Rodric M. Rabbah, Saman P. Amarasinghe |
A lightweight streaming layer for multicore execution. |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Bengt Jonsson |
State-space exploration for concurrent algorithms under weak memory orderings: (preliminary version). |
SIGARCH Computer Architecture News |
2008 |
DBLP DOI BibTeX RDF |
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")