Search results for "SIMD architecture"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Fouzhan Hosseini, Amir Fijany, Saeed Safari, Ryad Chellali, Jean-Guy Fontaine	Real-Time Parallel Implementation of SSD Stereo Vision Algorithm on CSX SIMD Architecture.	ISVC	2009	DBLP DOI BibTeX RDF
2	Jih-Ching Chiu, Yu-Liang Chou, Hua-Yi Tzeng	A multi-streaming SIMD architecture for multimedia applications.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	SIMD, streaming processing, streaming computing, processor-in-memory, mmx, multimedia extensions, pim
2	Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou	Design of a novel SIMD architecture by fusing operations and registers.	ICS	2009	DBLP DOI BibTeX RDF	processor-in-memory, mmx, simd, multimedia extensions, pim
2	Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck	A self-organizing defect tolerant SIMD architecture.	JETC	2007	DBLP DOI BibTeX RDF	Self-organizing, SIMD, data parallel, DNA, defect tolerance, nanocomputing, bit-serial
2	Kota Yamaguchi, Yoshihiro Watanabe, Takashi Komuro, Masatoshi Ishikawa	Design of a Massively Parallel Vision Processor based on Multi-SIMD Architecture.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Mohammed Sayed, Wael M. Badawy	An affine-based algorithm and SIMD architecture for video compression with low bit-rate applications.	IEEE Trans. Circuits Syst. Video Techn.	2006	DBLP DOI BibTeX RDF
2	Hoseok Chang, Junho Cho, Wonyong Sung	Performance Evaluation of an SIMD Architecture with a Multi-bank Vector Memory Unit.	SiPS	2006	DBLP DOI BibTeX RDF
2	Jaidev P. Patwardhan, Vijeta Johri, Chris Dwyer, Alvin R. Lebeck	A defect tolerant self-organizing nanoscale SIMD architecture.	ASPLOS	2006	DBLP DOI BibTeX RDF	self-organizing, SIMD, data parallel, DNA, defect tolerance, nanocomputing, bit-serial
2	Weihua Zhang, Tao Bao, Binyu Zang, Chuanqi Zhu	Data Pipeline Optimization for Shared Memory Multiple-SIMD Architecture.	LCPC	2006	DBLP DOI BibTeX RDF
2	Weihua Zhang, Xinglong Qian, Ye Wang, Binyu Zang, Chuanqi Zhu	Optimizing compiler for shared-memory multiple SIMD architecture.	LCTES	2006	DBLP DOI BibTeX RDF	multiple SIMD, optimization, locality, replication, shared memory
2	Nabil Ouerhani, Heinz Hügli, Pierre-Yves Burgi, Pierre-François Ruedi	A Real Time Implementation of the Saliency-Based Model of Visual Attention on a SIMD Architecture.	DAGM-Symposium	2002	DBLP DOI BibTeX RDF
2	Michael Meißner, S. Grimm, Wolfgang Straßer, J. Packer, Dairsie Latimer	Parallel volume rendering on a single-chip SIMD architecture.	IEEE Symposium on Parallel and Large-Data Visualization and Graphics	2001	DBLP BibTeX RDF	Parallel Processing, Volume Rendering, Ray Casting
2	Kuan-Hung Chen, Shi-Chung Chang, Tzi-Dar Chiueh, Peter B. Luh, Xing Zhao	SIMD architecture for job shop scheduling problem solving.	ISCAS	2001	DBLP DOI BibTeX RDF
2	Per Larsson-Edefors	A Miniature Serial-Data SIMD Architecture.	EUROMICRO	1998	DBLP DOI BibTeX RDF
2	Marco Mattavelli, Sylvain Brunetton, Daniel Mlynek	A Parallel Multimedia Processor for Macroblock Based Compression Standards. (PDF / PS)	ICIP	1997	DBLP DOI BibTeX RDF	parallel multimedia processor, macroblock based compression standards, block-based video processing algorithms, DGP, digital generic processor, generic system architecture, pixel processors, RISC controller, video processing algorithms, video effects, window clipping, H.261, 1.7 GIPS, 54 MHz, 0.5 micron, code, video compression, digital filtering, MPEG-2, digital signal processing chips, H.263, SIMD architecture, MPEG-1
2	Youngmin Hur, Stephen A. Szygenda	Special purpose array processor for digital logic simulation.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	special purpose array processor, digital logic simulation, large VLSI circuits, compute-intensive tasks, digital analysis, time driven array processor, massively parallel processing element, compiled event-driven technology, nominal transport delay timing analysis, delay time order, levelized circuit, massively parallel PE array, MARS accelerator, VLSI, parallel architectures, delays, timing, fault simulation, logic CAD, digital simulation, circuit analysis computing, special purpose computers, SIMD architecture, hardware cost
2	Wieslaw Lucjan Nowinski	A SIMD Architecture for Medical Imaging.	CONPAR	1992	DBLP DOI BibTeX RDF
2	Lorenz A. Schmitt, Stephen S. Wilson	The AIS-5000 Parallel Processor.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	AIS-5000, parallel memory organization, image-based algorithms, computer vision, computer vision, parallel architecture, parallel architectures, computerised picture processing, computerised picture processing, microprocessor chips, parallel processor, SIMD architecture
1	Wing-Yee Lo, Daniel Pak-Kong Lun, Wan-Chi Siu, Wendong Wang, Jiqiang Song	Improved SIMD Architecture for High Performance Video Processors.	IEEE Trans. Circuits Syst. Video Techn.	2011	DBLP DOI BibTeX RDF
1	Dong-hwan Lee, Wonyong Sung	Multi-core and SIMD architecture based implementation of recursive digital filtering algorithms.	ICASSP	2010	DBLP DOI BibTeX RDF
1	Fouzhan Hosseini, Amir Fijany, Jean-Guy Fontaine	Highly Parallel Implementation of Harris Corner Detector on CSX SIMD Architecture.	Euro-Par Workshops	2010	DBLP DOI BibTeX RDF
1	Stéphane Chevobbe, Suresh Pajaniradja, Laurent Letellier	Exploration platform of embedded simd architecture for autonomous retinas.	DASIP	2010	DBLP DOI BibTeX RDF
1	Amir Hormati, Yoonseo Choi, Mark Woh, Manjunath Kudlur, Rodric M. Rabbah, Trevor N. Mudge, Scott A. Mahlke	MacroSS: macro-SIMDization of streaming applications.	ASPLOS	2010	DBLP DOI BibTeX RDF	optimization, compiler, streaming, SIMD architecture
1	Sangwon Seo, Ronald G. Dreslinski, Mark Woh, Chaitali Chakrabarti, Scott A. Mahlke, Trevor N. Mudge	Diet SODA: a power-efficient processor for digital cameras.	ISLPED	2010	DBLP DOI BibTeX RDF	digital still cameras, near-threshold, dynamic voltage scaling, SIMD
1	Jakub Kurzak, Wesley Alvaro, Jack Dongarra	Optimizing matrix multiplication for a short-vector SIMD architecture - CELL processor.	Parallel Computing	2009	DBLP DOI BibTeX RDF
1	Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama	A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic.	ERSA	2009	DBLP BibTeX RDF
1	Vibhav Vineet, Pawan Harish, Suryakant Patidar, P. J. Narayanan	Fast minimum spanning tree for large graphs on the GPU.	High Performance Graphics	2009	DBLP DOI BibTeX RDF
1	Manuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	A SIMD optimization framework for retargetable compilers.	TACO	2009	DBLP DOI BibTeX RDF	SIMD, vectorization, ASIP, subword parallelism, retargetable compilers
1	Hoseok Chang, Junho Cho, Wonyong Sung	Compiler-Based Performance Evaluation of an SIMD Processor with a Multi-Bank Memory Unit.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Multi-bank memory, Vectorizing compiler, Data allocation, On-chip memory, SIMD processor
1	Yifan He, Zoran Zivkovic, Richard P. Kleihorst, Alexander Danilin, Henk Corporaal	Real-time implementations of Hough Transform on SIMD architecture.	ICDSC	2008	DBLP DOI BibTeX RDF
1	Radoslaw Mantiuk, Dawid Pajak	Acceleration of High Dynamic Range Imaging Pipeline Based on Multi-threading and SIMD Technologies.	ICCS	2008	DBLP DOI BibTeX RDF	multi-threading architecture, computer visualization, image processing, high dynamic range imaging, SIMD architecture, SSE
1	Philippe Bonnot, Fabrice Lemonnier, Gilbert Edelin, Gerard Gaillat, Olivier Ruch, Pascal Gauget	Definition and SIMD Implementation of a Multi-Processing Architecture Approach on FPGA.	DATE	2008	DBLP DOI BibTeX RDF
1	Raymond Frijns, Hamed Fatemi, Bart Mesman, Henk Corporaal	DC-SIMD : Dynamic communication for SIMD processors.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Vaibhav Saxena, Prashant Agrawal, Yogish Sabharwal, Vijay K. Garg, Vimitha A. Kuruvilla, John A. Gunnels	Optimization of BLAS on the Cell Processor.	HiPC	2008	DBLP DOI BibTeX RDF	Direct Memory Access (DMA), multi-core, linear algebra, BLAS, Cell processor
1	Jung-Min Park, Jung-Wook Park, Cheong-Ghil Kim, Gi-Ho Park, Shin-Dug Kim	An efficient scheme for parallelizing fast search algorithm on SIMD architecture in H.264/AVC.	ISCA PDCS	2007	DBLP BibTeX RDF
1	Jianying Peng, Xing Qin, Dexian Li, Xiaolang Yan, Xiexiong Chen	An Efficient SIMD Architecture with Parallel Memory for 2D Cosine Transforms of Video Coding.	ASAP	2007	DBLP DOI BibTeX RDF
1	Chen Wu, Hamid K. Aghajan, Richard P. Kleihorst	Mapping Vision Algorithms on SIMD Architecture Smart Cameras.	ICDSC	2007	DBLP DOI BibTeX RDF
1	Philippe Marquet, Simon Duquennoy, Sébastien Le Beux, Samy Meftali, Jean-Luc Dekeyser	Massively parallel processing on a chip.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	MasPar, mppSoC, SoC, SIMD, system-on-a-chip, massively parallelism
1	Tirath Ramdas, Gregory K. Egan, David Abramson, Kim Baldridge	Converting massive TLP to DLP: a special-purpose processor for molecular orbital computations.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	thread-level parallelism, content-addressable memory, vector processing, address generation, data-level parallelism
1	Shorin Kyo, Takuya Koga, Hanno Lieske, Shouhei Nomoto, Shin'ichiro Okazaki	A low-cost mixed-mode parallel processor architecture for embedded systems.	ICS	2007	DBLP DOI BibTeX RDF	embedded systems, parallel architectures, SIMD, MIMD, multimedia processing, tile architectures, mixed-mode
1	Kyoko Iwasawa, Alan Mycroft	Choosing Method of the Most Effective Nested Loop Shearing for Parallelism.	PDCAT	2007	DBLP DOI BibTeX RDF
1	Mitsuru Matsui, Junko Nakajima	On the Power of Bitslice Implementation on Intel Core2 Processor.	CHES	2007	DBLP DOI BibTeX RDF	Fast Software Encryption, Bitslice, KASUMI, Core2, AES
1	Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Basten, Richard P. Kleihorst	RC-SIMD: Reconfigurable communication SIMD architecture for image processing applications.	J. Embedded Computing	2006	DBLP BibTeX RDF
1	Olivier Muller, Amer Baghdadi, Michel Jézéquel	ASIP-based multiprocessor SoC design for simple and double binary turbo decoding.	DATE	2006	DBLP DOI BibTeX RDF
1	Nico Galoppo, Miguel A. Otaduy, Paul Mecklenburg, Markus H. Gross, Ming C. Lin	Fast simulation of deformable models in contact using dynamic deformation textures.	Symposium on Computer Animation	2006	DBLP DOI BibTeX RDF
1	Charles T. Loop, Jim Blinn	Real-time GPU rendering of piecewise algebraic surfaces.	ACM Trans. Graph.	2006	DBLP DOI BibTeX RDF	Bézier tetrahedra, algebraic surface rendering, implicit surface rendering, GPU algorithms
1	Mahdi Nazm Bojnordi, Mehdi Semsarzadeh, Mahmoud Reza Hashemi, Omid Fatemi	Efficient Hardware Implementation for H.264/AVC Motion Estimation.	APCCAS	2006	DBLP DOI BibTeX RDF
1	C. J. Duanmu	Accelearation of Full-Search Algorithm on SIMD Architectures by Using Eight-Bit Partial Sums of Four Luminance Values.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Basten, Pieter P. Jonker	Run-time reconfiguration of communication in SIMD architectures.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Mohammed Sayed, Ihab Amer, Wael M. Badawy	Towards an H.264/AVC full encoder on chip: an efficient real-time VBSME ASIC chip.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Carlos A. Alba Pinto, Aleksandar Beric, Satendra Pal Singh, Sachin Farfade	HiveFlex-Video VSP1: Video Signal Processing Architecture for Video Coding and Post-Processing.	ISM	2006	DBLP DOI BibTeX RDF
1	Zhiyu He, Falko Kuester	GPU-Based Active Contour Segmentation Using Gradient Vector Flow.	ISVC	2006	DBLP DOI BibTeX RDF
1	Nigel C. Paver, Moinul H. Khan, B. C. Aldrich, C. D. Emmons	Accelerating Mobile Video: A 64-Bit SIMD Architecture for Handheld Applications.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	architecture, SIMD, SOC, multi-media, wireless video
1	Robert Geist, Jacob Hicks, Mark Smotherman, James Westall	Parallel simulation of petri nets on desktop pc hardware.	Winter Simulation Conference	2005	DBLP DOI BibTeX RDF
1	Kyusik Chung, Donghyun Kim, Lee-Sup Kim	A 3-way SIMD engine for programmable triangle setup in embedded 3D graphics hardware.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Jongmyon Kim, D. Scott Wills, Linda M. Wills	Determining Optimal Grain Size for Efficient Vector Processing on SIMD Image Processing Architectures.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
1	Jacek Mazurkiewicz	Systolic Realization of Kohonen Neural Network.	ICANN	2005	DBLP DOI BibTeX RDF
1	Dongsun Kim, Hyunsik Kim, Hong-Sik Kim, Gunhee Han, Duckjin Chung	A SIMD Neural Network Processor for Image Processing.	ISNN	2005	DBLP DOI BibTeX RDF
1	Ugo Erra	Toward Real Time Fractal Image Compression Using Graphics Hardware.	ISVC	2005	DBLP DOI BibTeX RDF
1	Maria Charalambous, Pedro Trancoso, Alexandros Stamatakis	Initial Experiences Porting a Bioinformatics Application to a Graphics Processor.	Panhellenic Conference on Informatics	2005	DBLP DOI BibTeX RDF
1	Ali R. Iranpour, Krzysztof Kuchcinski	Evaluation of SIMD Architecture Enhancement in Embedded Processors for MPEG-4.	DSD	2004	DBLP DOI BibTeX RDF
1	Antonio Gentile, D. Scott Wills	Portable Video Supercomputing.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
1	Nabil Ouerhani, Heinz Hügli	Real-time visual attention on a massively parallel SIMD architecture.	Real-Time Imaging	2003	DBLP DOI BibTeX RDF
1	Haitao Du, Marcos Sanchez-Elez, Nozar Tabrizi, Nader Bagherzadeh, Manuel L. Anido, Milagros Fernández	Interactive Ray Tracing on Reconfigurable SIMD MorphoSys.	DATE	2003	DBLP DOI BibTeX RDF
1	Mohammed Sayed, Wael M. Badawy	A New Class of Computational RAM Architectures for Real-Time MPEG-4 Applications.	IWSOC	2003	DBLP DOI BibTeX RDF
1	Salvatore Vitabile, Antonio Gentile, G. B. Dammone, Filippo Sorbello	MLP Neural Network Implementation on a SIMD Architecture.	WIRN	2002	DBLP DOI BibTeX RDF	Automatic Road Sign Recognition System, SIMD Pixel Processor
1	Kwang-Sook Kim, Cheong-Ghil Kim, Shin-Dug Kim	A Hierarchical Multiple SIMD Architecture for Artificial Neural Networks.	IASTED PDCS	2002	DBLP BibTeX RDF
1	Bogdan J. Falkowski	Calculation of Walsh transform on MasPar computer.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Manuel L. Anido, Nader Bagherzadeh, Nozar Tabrizi, Haitao Du, Marcos Sanchez-Elez	Interactive Ray Tracing Using a SIMD Reconfigurable Architecture.	SBAC-PAD	2002	DBLP DOI BibTeX RDF
1	Tetsuya Izu, Tsuyoshi Takagi	Fast Elliptic Curve Multiplications with SIMD Operations.	ICICS	2002	DBLP DOI BibTeX RDF	NAF, SIMD operations, side channel attacks, Elliptic Curve Cryptosystems (ECC), scalar multiplication, window method
1	Omar Bouattane, Jelloul Elmesbahi, M. Khaldoun, A. Rami	A Fast Algorithm for k-Nearest Neighbor Problem on a Reconfigurable Mesh Computer.	Journal of Intelligent and Robotic Systems	2001	DBLP DOI BibTeX RDF	reconfigurable mesh computer, parallel processing, data analysis, k-nearest neighbor, SIMD architecture
1	Antonio Gentile, D. Scott Wills	Impact of Pixel per Processor Ratio on Embedded SIMD Architectures.	ICIAP	2001	DBLP DOI BibTeX RDF
1	Kazumaro Aoki, Fumitaka Hoshino, Tetsutaro Kobayashi, Hiroaki Oguro	Elliptic Curve Arithmetic Using SIMD.	ISC	2001	DBLP DOI BibTeX RDF
1	Alessandro Lonardo, Emanuele Panizzi, Benedetto Proietti	C++ programming language for an abstract massively parallel SIMD architecture	CoRR	2000	DBLP BibTeX RDF
1	Yong Zhang, Kai-Kuang Ma, Qingdong Yao	Novel video signal processor with VLIW-controlled SIMD architecture.	VCIP	2000	DBLP BibTeX RDF
1	Kohtaro Ohba, Jesus Carlos Pedraza Ortega, Kazuo Tanie, Gakuyoshi Rin, Ryoichi Dangi, Yoshinori Takei, Takeshi Kaneko, Nobuaki Kawahara	Real-Time Micro Environmental Observation with Virtual Reality.	ICPR	2000	DBLP DOI BibTeX RDF
1	Zhang Yong, Min Zhang	A Novel Superscalar Architecture for Fast DCT Implementation.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
1	G. K. Grigoriadis, Basil G. Mertzios, V. D. Tourassis	Fast implementation of robot inverse dynamics with distributed arithmetic via a SIMD architecture.	IEEE Transactions on Systems, Man, and Cybernetics, Part A	1999	DBLP DOI BibTeX RDF
1	Hyung Lee, Kyung-Ae Moon, Jong-Won Park	Design of Parallel Processing System for Facial Image Retrieval.	ACPC	1999	DBLP DOI BibTeX RDF
1	Sanjay V. Rajopadhye, Claude Tadonki, Tanguy Risset	The Algebraic Path Problem Revisited.	Euro-Par	1999	DBLP DOI BibTeX RDF	Warshall-Floyd & Gauss-Jordan elimination, systolic synthesis, recurrence equations, scheduling, shortest path, transitive closure, matrix inversion, space-time mapping
1	S. Nicastro, F. Valentinotti	Parallel Implementation of a Meteorological Model on a SIMD Architecture.	HPCN	1998	DBLP DOI BibTeX RDF
1	Nael B. Abu-Ghazaleh, Philip A. Wilsey	Shared Control - Supporting Control Parallelism Using a SIMD-like Architecture.	Euro-Par	1998	DBLP DOI BibTeX RDF
1	Eugene V. Zima	Fast Parallel Computation of the Polynomial Shift. (PDF / PS)	IPPS	1997	DBLP DOI BibTeX RDF
1	Karen Egiazarian, Jaakko Astola	On Generalized Fibonacci Cubes and Unitary Transforms.	Appl. Algebra Eng. Commun. Comput.	1997	DBLP DOI BibTeX RDF	Boolean cube, Zeckendorf 's representation, Unitary transforms, Fast algorithms, Fibonacci cube
1	Pascal Faudemay, Laurent Winckel	An Abstract Model for a Low Cost SIMD Architecture. (PDF / PS)	ASAP	1996	DBLP DOI BibTeX RDF
1	A. B. Della Rocca, L. La Porta, F. Valentinotti	Radiographic Process Simulation by Integration of Boltzmann Equation on SIMD Architecture (Quadrics QH 4).	HPCN	1996	DBLP DOI BibTeX RDF
1	Maurizio Rebaudengo, Matteo Sonza Reorda	A Cellular Genetic Algorithm for the Floorplan Area Optimization Problem on a SIMD Architecture.	HPCN	1996	DBLP DOI BibTeX RDF
1	Antonio Gentile, Huy Cat, Faouzi Kossentini, Filippo Sorbello, D. Scott Wills	Real-Time Implementation of Full-Search Vector Quantization on a Low Memory SIMD Architecture.	Data Compression Conference	1996	DBLP DOI BibTeX RDF
1	Tudor Jebelean	Integer and Rational Arithmetic on MasPar.	DISCO	1996	DBLP DOI BibTeX RDF
1	Fabienne Jézéquel	A Time and Space Parallel Algorithm for the Heat Equation: The Implicit Collocation Method.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF
1	Marek T. Michalewicz, Mark Priebatsch	Perfect Scaling of the Electronic Structure Problem on a SIMD Architecture.	Parallel Computing	1995	DBLP DOI BibTeX RDF
1	Myung Hoon Sunwoo, Soohwan Ong, Byungdug Ahn, Kyungwoo Lee	Design and Implementation of a Parallel Image Processor Chip for a SIMD Array Processor.	ASAP	1995	DBLP DOI BibTeX RDF	SIMD Array Processors, ASIC Chip, Image Processing, VLSI Design, VLSI Architectures
1	Mattias Johannesson	FFTs on a Linear SIMD Arrat.	Euro-Par	1995	DBLP DOI BibTeX RDF
1	Martin Neschen, Martin Gumm	A Scalable Bit-Sequential SIMD Architecture for Pattern Recognition.	PARLE	1994	DBLP DOI BibTeX RDF
1	Anders Åström, Folke Isaksson	Real-time Geometric Distortion Correction and Image Processing on the 1D SIMD architecture IVIP.	MVA	1994	DBLP BibTeX RDF
1	Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin	Area Time Trade-Offs in Micro-Grain VLSI Array Architectures.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	area time trade-offs, micro-grain VLSI array architectures, massively parallel control-flow architectures, associative memory architecture, Mux-based SIMD architecture, systolic MIMD/MISD computation, data-flow requirements, performance evaluation, performance, VLSI, parallel architectures, FFT, matrix multiplication, RAMs
1	Charles W. Anderson, Saikumar V. Devulapalli, Erik A. Stolz	EEG as a means of communication: preliminary experiments in EEG analysis using neural networks.	ASSETS	1994	DBLP DOI BibTeX RDF
1	Tudor Jebelean	Systolic Algorithms for Long Integer GCD Computation.	CONPAR	1994	DBLP DOI BibTeX RDF
1	Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri	Design of a massively parallel SIMD architecture for the Boltzmann machine.	Microprocessing and Microprogramming	1993	DBLP DOI BibTeX RDF
1	Myung Hoon Sunwoo, J. K. Aggarwal	A Sliding Memory Plane Array Processor.	IEEE Trans. Parallel Distrib. Syst.	1993	DBLP DOI BibTeX RDF	sliding memory, plane array processor, mesh-connected, single-input multiple-data, SliM, image processing, image processing, parallel architectures