Search results for "SRAM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
6	Jian Liu, Rafic Z. Makki	Power supply current detectability of SRAM defects.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	short-circuit currents, fault currents, power supply circuits, power supply current detectability, SRAM defects, SRAM cell, power supply current, I/sub DDQ/, quiescent power supply current, i/sub DDT/, transient power supply current, shorts, disturb-type pattern sensitivity, total current leakage, SRAM size, current detectability, large circuit effects, simulation, fault diagnosis, leakage currents, transients, SRAM chips, open defects, electric current measurement, physical defect
5	Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy	A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM.	ISLPED	2007	DBLP DOI BibTeX RDF	low power SRAM, low voltage SRAM, schmitt trigger, subthreshold SRAM, process variations
5	Chen-Huan Chiang, Sandeep K. Gupta	BIST TPG for SRAM cluster interconnect testing at board level.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing
4	Sreeharsha Tavva, Dhireesha Kudithipudi	Variation tolerant 9T SRAM cell design.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	bitline leakage, static random access memory (SRAM), process variations, static noise margin, embedded sram
4	Jaydeep P. Kulkarni, Keejong Kim, Sang Phill Park, Kaushik Roy	Process variation tolerant SRAM array for ultra low voltage applications.	DAC	2008	DBLP DOI BibTeX RDF	Schmitt trigger SRAM, low voltage/sub-threshold SRAM, process tolerance
4	Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto	A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering.	ISLPED	2006	DBLP DOI BibTeX RDF	data-bit reordering, low power SRAM, two-port SRAM, real-time image processing, majority logic
4	Yuki Yamagata, Kenichi Ichino, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Masayuki Satoh, Hiroyuki Itabashi, Takashi Murai, Nobuyuki Otsuka	Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	SRAM test, SRAM-based reconfigurable cell, memory tester, marching test
4	Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin	A built-in self-test and self-diagnosis scheme for embedded SRAM.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	self-diagnosis scheme, fault diagnosis, fault diagnosis, built-in self test, built-in self-test, system-on-chip, memory test, SRAM chips, embedded SRAM
4	Ding-Ming Kwai, Hung-Wen Chang, Hung-Jen Liao, Ching-Hua Chiao, Yung-Fa Chou	etection of SRAM cell stability by lowering array supply voltage.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cell stability detection, array supply voltage reduction, design-for-test technique, static random access memory, memory array, test mode, detection capability, logic testing, integrated circuit testing, design for testability, CMOS technology, SRAM chips, CMOS memory circuits, DFT technique, circuit stability, 0.18 micron
4	H. Goto, S. Nakamura, K. Iwasaki	Experimental fault analysis of 1 Mb SRAM chips.	VTS	1997	DBLP DOI BibTeX RDF	stuck-at cell faults, stuck-at bit-line faults, stuck-at word-line fault, neighborhood-pattern-sensitive faults, load capacity, margin fault detection, 1 Mbit, 70 C, 30 pF, memory testing, fault analysis, SRAM chips, SRAM chips
4	Hari Balachandran, D. M. H. Walker	Improvement of SRAM-based failure analysis using calibrated Iddq testing.	VTS	1996	DBLP DOI BibTeX RDF	defect-bitmap dictionary, voltage testing, microprocessor cache memory, integrated circuit testing, calibration, calibration, SRAM, cache storage, failure analysis, failure analysis, IDDQ testing, current testing, defect classification, SRAM chips, integrated circuit yield, integrated circuit yield
4	Bradly K. Fawcett, J. Watson	Reconfigurable Processing With Field Programmable Gate Arrays.	ASAP	1996	DBLP DOI BibTeX RDF	reconfigurable processing, internal architecture, computationally-intensive tasks, programmable solution, XC6200 FPGA architecture, SRAM control store, on-chip memory capability, field programmable gate arrays, interconnections, reconfigurable architectures, processors, coprocessors, coprocessors, SRAM chips, SRAM-based field programmable gate arrays
3	Anuj Pushkarna, Hamid Mahmoodi	Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	reliability, aging, SRAM, power gating
3	Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan	A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	nano-CMOS, power, leakage, SRAM, static noise margin
3	Paul Zuber, Petr Dobrovolný, Miguel Miranda	A holistic approach for statistical SRAM analysis.	DAC	2010	DBLP DOI BibTeX RDF	statistical SRAM analysis, process variability, yield prediction
3	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	A statistical simulation method for reliability analysis of SRAM core-cells.	DAC	2010	DBLP DOI BibTeX RDF	SRAM core-cell, Monte-Carlo, reliability analysis
3	Srivatsan Chellappa, Jia Ni, Xiaoyin Yao, Nathan D. Hindman, Jyothi Velamala, Min Chen, Yu Cao, Lawrence T. Clark	In-situ characterization and extraction of SRAM variability.	DAC	2010	DBLP DOI BibTeX RDF	SRAM test, data retention voltage, threshold voltage variation, write margin, extraction
3	Adam C. Cabe, Zhenyu Qi, Mircea R. Stan	Stacking SRAM banks for ultra low power standby mode operation.	DAC	2010	DBLP DOI BibTeX RDF	stacked SRAM, low-power memory
3	Yong Zhang, Peng Li, Garng M. Huang	Separatrices in high-dimensional state space: system-theoretical tangent computation and application to SRAM dynamic stability analysis.	DAC	2010	DBLP DOI BibTeX RDF	separatrix, SRAM, dynamic stability
3	Satyanand Nalam, Mudit Bhargava, Ken Mai, Benton H. Calhoun	Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers.	DAC	2010	DBLP DOI BibTeX RDF	optimization, design space exploration, SRAM, virtual prototype, iterative design
3	Zhenyu Qi, Jiajing Wang, Adam C. Cabe, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun, Mircea R. Stan	SRAM-based NBTI/PBTI sensor system design.	DAC	2010	DBLP DOI BibTeX RDF	PBTI, sensor system design, sensor, redundancy, process variation, aging, yield, SRAM, NBTI
3	Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil Dutt	Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	multiple sleep mode, peripheral circuits, sram memory, temperature reduction, leakage power
3	Vita Pi-Ho Hu, Yu-Sheng Wu, Ming-Long Fan, Pin Su, Ching-Te Chuang	Design and analysis of ultra-thin-body SOI based subthreshold SRAM.	ISLPED	2009	DBLP DOI BibTeX RDF	poisson's equation, subthreshold SRAM, ultra-thin-body, soi, static noise margin
3	Ik Joon Chang, Debabrata Mohapatra, Kaushik Roy	A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors.	DAC	2009	DBLP DOI BibTeX RDF	low power SRAM, supply voltage over-scaling, graceful degradation
3	Jian Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi	SRAM parametric failure analysis.	DAC	2009	DBLP DOI BibTeX RDF	failure probability estimation, response surface model, SRAM, parametric failure
3	Rouwaida Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif	Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield.	ISQED	2008	DBLP DOI BibTeX RDF	decoupled design, 8T, 6T, stacked devices, stability, yield, sram, double gate
3	Huifang Qin, Animesh Kumar, Kannan Ramchandran, Jan M. Rabaey, Prakash Ishwar	Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation.	ISQED	2008	DBLP DOI BibTeX RDF	DRV, low power, ECC, leakage, SRAM, variation, low voltage, error tolerant
3	Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M. Rabaey, Kannan Ramchandran	Fundamental Data Retention Limits in SRAM Standby Experimental Results.	ISQED	2008	DBLP DOI BibTeX RDF	standby, data retention, low power, SRAM, error control code
3	Rouwaida Kanj, Zhuo Li, Rajiv V. Joshi, Frank Liu, Sani R. Nassif	A Root-Finding Method for Assessing SRAM Stability.	ISQED	2008	DBLP DOI BibTeX RDF	stability, memory, yield, sram, roots
3	Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto	Quality of a Bit (QoB): A New Concept in Dependable SRAM.	ISQED	2008	DBLP DOI BibTeX RDF	Quality of a bit, SRAM
3	Young-Gu Kim, Soo-Hwan Kim, Hoon Lim, Sanghoon Lee, Keun-Ho Lee, Young-Kwan Park, Moon-Hyun Yoo	The Statistical Failure Analysis for the Design of Robust SRAM in Nano-Scale Era.	ISQED	2008	DBLP DOI BibTeX RDF	Statistical failure analysis, DFM, SRAM
3	Bastien Giraud, Amara Amara	Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS.	DELTA	2008	DBLP DOI BibTeX RDF	SRAM cell, Double Gate (DG), Static Noise Margin (SNM), Write Margin (WM)
3	Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi	A low leakage 9t sram cell for ultra-low power operation.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	sram cell, low power, nanotechnology, leakage power, static noise margin
3	Maziar Goudarzi, Tohru Ishihara	Instruction cache leakage reduction by changing register operands and using asymmetric sram cells.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	asymmetric sram, leakage, instruction cache, register renaming
3	Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy	Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry.	VTS	2008	DBLP DOI BibTeX RDF	Design, yield, failure, SRAM, variation
3	Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin	An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing.	VTS	2008	DBLP DOI BibTeX RDF	write driver, design-for-diagnosis, diagnosis, SRAM
3	Mohammed Shareef I, Pradeep Nair, Bharadwaj Amrutur	Energy Reduction in SRAM using Dynamic Voltage and Frequency Management.	VLSI Design	2008	DBLP DOI BibTeX RDF	Delay Monitor, DVFM, Pareto optimal curve, Replica circuits, SRAM, Energy reduction, Energy monitor
3	Baker Mohammad, Martin Saint-Laurent, Paul Bassett, Jacob A. Abraham	Cache Design for Low Power and High Yield.	ISQED	2008	DBLP DOI BibTeX RDF	reduce voltage swing, sram yield, SRAM 6T cell, cache design, parametric failure
3	Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro	Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	reliability, fault tolerant systems, SEU, SRAM-based FPGA
3	Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang	A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies.	ISLPED	2007	DBLP DOI BibTeX RDF	booster circuit, low power, yield, SRAM
3	Keejong Kim, Hamid Mahmoodi, Kaushik Roy	A low-power SRAM using bit-line charge-recycling technique.	ISLPED	2007	DBLP DOI BibTeX RDF	write margin, write power, low power, process variation, SRAM, charge-recycling
3	Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang	Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies.	ISLPED	2007	DBLP DOI BibTeX RDF	FD/SOI, low-power, stability, SRAM
3	Luca Sterpone, Massimo Violante	A new decompression system for the configuration process of SRAM-based FPGAS.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	configuration mechanisms, compression algorithm, SRAM-based FPGA
3	Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar	Impact of NBTI on SRAM Read Stability and Design for Reliability.	ISQED	2006	DBLP DOI BibTeX RDF	Static Noise Margin (SNM), Reaction-Diffusion (R-D) Model, Cache, SRAM, Negative Bias Temperature Instability (NBTI)
3	Mohammad Sharifkhani, Manoj Sachdev	A low power SRAM architecture based on segmented virtual grounding.	ISLPED	2006	DBLP DOI BibTeX RDF	static-random access memory, write power reduction, low-power, SRAM, leakage reduction
3	Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim, Kaushik Roy	Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM.	DAC	2006	DBLP DOI BibTeX RDF	adaptive source biasing, hold failures, low power SRAM
3	Kanak Agarwal, Sani R. Nassif	Statistical analysis of SRAM cell stability.	DAC	2006	DBLP DOI BibTeX RDF	modeling, reliability, stability, SRAM, noise margin
3	Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif	Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events.	DAC	2006	DBLP DOI BibTeX RDF	statistical performance analysis, SRAM, yield prediction
3	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan	Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	SRAM core-cell, resistive open defects, memory testing, March test, dynamic faults
3	Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King, Borivoje Nikolic	FinFET-based SRAM design.	ISLPED	2005	DBLP DOI BibTeX RDF	double gate transistors, low power, memory, SRAM
3	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies.	DAC	2005	DBLP DOI BibTeX RDF	SRAM memories, VDSM technologies, core-cell, test, march test, dynamic faults, defect analysis
3	Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy	Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS.	VTS	2005	DBLP DOI BibTeX RDF	Failure mechanixm, Process Variation, DFT, SRAM, March Test
3	Josh Yang, Baosheng Wang, André Ivanov	Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode.	VLSI Design	2004	DBLP DOI BibTeX RDF	6T SRAM, Area Penalty, Write Recovery, Memory testing, Test Time, Open Defects
3	Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy	A forward body-biased low-leakage SRAM cache: device and architecture considerations.	ISLPED	2003	DBLP DOI BibTeX RDF	forward body-biasing, super high VT, SRAM, leakage power
3	Prabhat Jain, G. Edward Suh, Srinivas Devadas	Embedded intelligent SRAM.	DAC	2003	DBLP DOI BibTeX RDF	computation partitioning, embedded, SRAM, intelligent
3	Navid Azizi, Andreas Moshovos, Farid N. Najm	Low-leakage asymmetric-cell SRAM.	ISLPED	2002	DBLP DOI BibTeX RDF	low-leakage, low-power, SRAM, dual-Vt
3	Jeyran Hezavei, Narayanan Vijaykrishnan, Mary Jane Irwin	A comparative study of power efficient SRAM designs.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF	low power, decoder, SRAM
3	A. J. van de Goor, J. E. Simonse	Defining SRAM Resistive Defects and Their Simulation Stimuli.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Resistive defects, simulation stimuli, SRAM functional faults, SPICE simulation
3	A. M. Fahim, Muhammad M. Khellah, Mohamed I. Elmasry	A Low-Power High-Performance Embedded SRAM Macrocell.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	low power, memory, DSP, high performance, SRAM
2	Zhe Feng, Naifeng Jing, GengSheng Chen, Yu Hu, Lei He	IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs.	FPL	2011	DBLP DOI BibTeX RDF	in-place, soft error, don't care, mitigation, SRAM-based FPGA
2	Darsen D. Lu, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu	Compact Modeling of Variation in FinFET SRAM Cells.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	multigate MOSFETs, variability, design for manufacturing, SRAM, design and test, FinFET, compact modeling
2	Amara Amara, Bastien Giraud, Olivier Thomas	An Innovative 6T Hybrid SRAM Cell in sub-32 nm Double-Gate MOS Technology.	DELTA	2010	DBLP DOI BibTeX RDF	SRAM cell, Planar Double-Gate (DG), Fully Depleted SOI (FD-SOI), read and write tradeoffs, Ultra Low Voltage (ULV)
2	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	Impact of Resistive-Bridging Defects in SRAM Core-Cell.	DELTA	2010	DBLP DOI BibTeX RDF	core-cell, resistive-bridging defects, SRAM
2	Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto	0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM.	ISLPED	2010	DBLP DOI BibTeX RDF	fine-grain control, low power, cache memory, microarchitecture, variation, low voltage
2	Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj	FinFET SRAM Design.	VLSI Design	2010	DBLP DOI BibTeX RDF	variability, SRAM, FinFET, Double gate
2	Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan	A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM.	VLSI Design	2010	DBLP DOI BibTeX RDF	Nanoscale CMOS, SRAM, Power Dissipation, Static Noise Margin
2	Animesh Kumar, Jan M. Rabaey, Kannan Ramchandran	SRAM supply voltage scaling: A reliability perspective.	ISQED	2009	DBLP DOI BibTeX RDF
2	S. Lakshminarayanan, J. Joung, G. Narasimhan, R. Kapre, M. Slanina, J. Tung, M. Whately, C.-L. Hou, W.-J. Liao, S.-C. Lin, P.-G. Ma, C.-W. Fan, M.-C. Hsieh, F.-C. Liu, K.-L. Yeh, W.-C. Tseng, S. W. Lu	Standby power reduction and SRAM cell optimization for 65nm technology.	ISQED	2009	DBLP DOI BibTeX RDF
2	Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi	The impact of BEOL lithography effects on the SRAM cell performance and yield.	ISQED	2009	DBLP DOI BibTeX RDF
2	Soner Yaldiz, Umut Arslan, Xin Li, Larry T. Pileggi	Efficient statistical analysis of read timing failures in SRAM circuits.	ISQED	2009	DBLP DOI BibTeX RDF
2	Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto	A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme.	ISQED	2009	DBLP DOI BibTeX RDF
2	Yu-Hsun Lin, Xuan-Yi Lin, Yeh-Ching Chung	Reducing Leakage Power of JPEG Image on Asymmetric SRAM.	CSE	2009	DBLP DOI BibTeX RDF
2	Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri	Low power and high performance sram design using bank-based selective forward body bias.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	low power, high performance, body bias
2	David Hentrich, Erdal Oruklu, Jafar Saniie	Performance evaluation of SRAM cells in 22nm predictive CMOS technology.	EIT	2009	DBLP DOI BibTeX RDF
2	Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro López, José Duato	An hybrid eDRAM/SRAM macrocell to implement first-level data caches.	MICRO	2009	DBLP DOI BibTeX RDF	retention time, static and dynamic memory cells, leakage current
2	Minki Cho, Jason Schlessman, Wayne Wolf, Saibal Mukhopadhyay	Accuracy-aware SRAM: a reconfigurable low power SRAM architecture for mobile multimedia applications.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Kuande Wang, Li Chen, Jinsheng Yang	AN ultra low power fault tolerant SRAM design in 90nm CMOS.	CCECE	2009	DBLP DOI BibTeX RDF
2	Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto	A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection.	VLSI Design	2009	DBLP DOI BibTeX RDF
2	Luca Sterpone	Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs.	ARC	2009	DBLP DOI BibTeX RDF	fault tolerance, FPGA, Single Event Upset, Triple Modular Redundancy, Timing-driven Placement
2	Xin He, Jorgen Peddersen, Sri Parameswaran	LOP: a novel SRAM-based architecture for low power and high throughput packet classification.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	low-power, packet classification, hardware design
2	Viktor Pus, Jan Korenek	Fast and scalable packet classification using perfect hash functions.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, sram, packet classification
2	Kiyoo Itoh	Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era.	ISLPED	2009	DBLP DOI BibTeX RDF	0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet
2	Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, Leland Chang, Steven J. Koester, Dennis Sylvester, David Blaauw	Low power circuit design based on heterojunction tunneling transistors (HETTs).	ISLPED	2009	DBLP DOI BibTeX RDF	SRAM design, low power applications, tunneling transistor
2	Weirong Jiang, Viktor K. Prasanna	Field-split parallel architecture for high performance multi-match packet classification using FPGAs.	SPAA	2009	DBLP DOI BibTeX RDF	multi-match packet classification, fpga, sram, nids
2	Björn Osterloh, Harald Michalik, Björn Fiethe	SoCWire: A Robust and Fault Tolerant Network-on-Chip Approach for a Dynamic Reconfigurable System-on-Chip in FPGAs.	ARCS	2009	DBLP DOI BibTeX RDF	SoCWire, dynamic reconfigurable system, Sytem-on-Chip, Network-on-Chip, SRAM-based FPGA, VMC
2	Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy	Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	D. E. Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek K. De	Accurate Estimation of SRAM Dynamic Stability.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Kanak Agarwal, Sani R. Nassif	The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Zhiyu Liu, Volkan Kursun	Characterization of a Novel Nine-Transistor SRAM Cell.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Ke Xu, Chiu-sing Choy	A Five-Stage Pipeline, 204 Cycles/MB, Single-Port SRAM-Based Deblocking Filter for H.264/AVC.	IEEE Trans. Circuits Syst. Video Techn.	2008	DBLP DOI BibTeX RDF
2	Egas Henes Neto, Gilson I. Wirth, Fernanda Lima Kastensmidt	Mitigating Soft Errors in SRAM Address Decoders Using Built-in Current Sensors.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Fault-tolerance, Reliability, Testing, Built-in tests, Error-checking
2	Mark Lysinger, François Jacquet, Mehdi Zamanian, David McClure, Philippe Roche, Naren Sahoo, John Russell	A Radiation Hardened Nano-Power 8Mb SRAM in 130nm CMOS.	ISQED	2008	DBLP DOI BibTeX RDF	Rad Hard
2	Zhiyu Liu, Sherif A. Tawfik, Volkan Kursun	Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations.	ISQED	2008	DBLP DOI BibTeX RDF	static noise margin distribution, robust operation, active power, standby power distribution, double gate MOSFET, process variations, Cache memory
2	Hoang Le, Weirong Jiang, Viktor K. Prasanna	Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA.	FPL	2008	DBLP DOI BibTeX RDF
2	Florian Bauer, Georg Georgakos, Doris Schmitt-Landsiedel	A Design Space Comparison of 6T and 8T SRAM Core-Cells.	PATMOS	2008	DBLP DOI BibTeX RDF
2	Weirong Jiang, Viktor K. Prasanna	Parallel IP lookup using multiple SRAM-based pipelines.	IPDPS	2008	DBLP DOI BibTeX RDF
2	Tadayoshi Enomoto, Yuki Higuchi	A low-leakage current power 180-nm CMOS SRAM.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Chenjie Gu, Jaijeet S. Roychowdhury	An efficient, fully nonlinear, variability-aware non-monte-carlo yield estimation procedure with applications to SRAM cells and ring oscillators.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Hoang Le, Weirong Jiang, Viktor K. Prasanna	A SRAM-based Architecture for Trie-based IP Lookup Using FPGA.	FCCM	2008	DBLP DOI BibTeX RDF