Search results for "SRAM design"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, Leland Chang, Steven J. Koester, Dennis Sylvester, David Blaauw	Low power circuit design based on heterojunction tunneling transistors (HETTs).	ISLPED	2009	DBLP DOI BibTeX RDF	SRAM design, low power applications, tunneling transistor
2	Huifang Qin, Animesh Kumar, Kannan Ramchandran, Jan M. Rabaey, Prakash Ishwar	Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation.	ISQED	2008	DBLP DOI BibTeX RDF	DRV, low power, ECC, leakage, SRAM, variation, low voltage, error tolerant
2	Behnam Amelifard, Massoud Pedram, Farzan Fallah	Low-leakage SRAM Design with Dual V_t Transistors.	ISQED	2006	DBLP DOI BibTeX RDF
2	Qikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy	Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design.	DATE	2006	DBLP DOI BibTeX RDF
2	Jordan Lai	SRAM Design Techniques for Sub-nano CMOS Technology.	MTDT	2006	DBLP DOI BibTeX RDF
2	Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King, Borivoje Nikolic	FinFET-based SRAM design.	ISLPED	2005	DBLP DOI BibTeX RDF	double gate transistors, low power, memory, SRAM
2	Jun-Cheol Park, Vincent John Mooney III	Pareto Points in SRAM Design Using the Sleepy Stack Approach.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
2	Ramy E. Aly, Mohamed A. Elgamel, Magdy A. Bayoumi	Dual sense amplified bit lines (DSABL) architecture for low-power SRAM design.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Jaydeep P. Kulkarni, Kaushik Roy	Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Eric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih Hamzaoglu, Uddalak Bhattacharya, Kevin Zhang, Kaizad Mistry, Mark Bohr	A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Je-Hoon Lee, Young-Jun Song, Sang-Choon Kim	A Self-Timed SRAM Design for Average-Case Performance.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Rajiv V. Joshi, Rouwaida Kanj, V. Ramadurai	A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Fatih Hamzaoglu, Yih Wang, Pramod Kolar, Liqiong Wei, Yong-Gee Ng, Uddalak Bhattacharya, Kevin Zhang	Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF
1	Xuebei Yang, Kartik Mohanram	Robust 6T Si tunneling transistor SRAM design.	DATE	2011	DBLP DOI BibTeX RDF
1	Aravind Rajendran, Yuriy Shiyanovskii, Frank Wolff, Christos A. Papachristou	Noise margin, critical charge and power-delay tradeoffs for SRAM design.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Yuriy Shiyanovskii, Aravind Rajendran, Christos A. Papachristou	A novel radiation tolerant SRAM design based on synergetic functional component separation for nanoscale CMOS.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Akshit Dayal, Peng Li, Garng M. Huang	Robust SRAM Design via Joint Sizing and Voltage Optimization Under Dynamic Stability Constraints.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Yih Wang, Uddalak Bhattacharya, Fatih Hamzaoglu, Pramod Kolar, Yong-Gee Ng, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr	A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management.	J. Solid-State Circuits	2010	DBLP DOI BibTeX RDF
1	Gregory K. Chen, Dennis Sylvester, David Blaauw, Trevor N. Mudge	Yield-Driven Near-Threshold SRAM Design.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Yngvar Berg, Tuan Vu Cao	New SRAM design using body bias technique for ultra low power applications.	ISQED	2010	DBLP DOI BibTeX RDF
1	Touqeer Azam, Binjie Cheng, David R. S. Cumming	Variability resilient low-power 7T-SRAM design for nano-scaled technologies.	ISQED	2010	DBLP DOI BibTeX RDF
1	J. Singh, Krishnan Ramakrishnan, S. Mookerjea, Suman Datta, Narayanan Vijaykrishnan, D. K. Pradhan	A novel si-tunnel FET based SRAM design for ultra low-power 0.3V VDD applications.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj	FinFET SRAM Design.	VLSI Design	2010	DBLP DOI BibTeX RDF	variability, SRAM, FinFET, Double gate
1	Borivoje Nikolic, Changhwan Shin, Min Hee Cho, Xin Sun, Tsu-Jae King Liu, Bich-Yen Nguyen	SRAM design in fully-depleted SOI technology.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Satyanand Nalam, Mudit Bhargava, Ken Mai, Benton H. Calhoun	Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers.	DAC	2010	DBLP DOI BibTeX RDF	optimization, design space exploration, SRAM, virtual prototype, iterative design
1	Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan	A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	nano-CMOS, power, leakage, SRAM, static noise margin
1	Toby Doorn, Roelof Salters	Robust Low Power Embedded SRAM Design: From System to Memory Cell.	PATMOS	2009	DBLP DOI BibTeX RDF
1	Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri	Low power and high performance sram design using bank-based selective forward body bias.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	low power, high performance, body bias
1	Yih Wang, Uddalak Bhattacharya, Fatih Hamzaoglu, Pramod Kolar, Yong-Gee Ng, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr	A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management.	ISSCC	2009	DBLP DOI BibTeX RDF
1	Kuande Wang, Li Chen, Jinsheng Yang	AN ultra low power fault tolerant SRAM design in 90nm CMOS.	CCECE	2009	DBLP DOI BibTeX RDF
1	Lin Liu, Yuanfu Zhao, Suge Yue	3D Simulation of Charge Collection and MNU in Highly-Scaled SRAM Design.	NCM	2009	DBLP DOI BibTeX RDF	charge collection, hardened cells, multiple-node upset (MNU), parasitic bipolar conduction
1	Jian Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi	SRAM parametric failure analysis.	DAC	2009	DBLP DOI BibTeX RDF	failure probability estimation, response surface model, SRAM, parametric failure
1	Kevin Zhang	Circuit design in nano-scale CMOS era: opportunities & challenges.	ISLPED	2009	DBLP DOI BibTeX RDF	VLSI, CMOS, circuit
1	Shin-ichi O'Uchi, Meishoku Masahara, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Kunihiro Sakamoto, Toshihiro Sekigawa, Hanpei Koike, Eiichi Suzuki	FinFET-Based Flex-Vth SRAM Design for Drastic Standby-Leakage-Current Reduction.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Deblina Sarkar, Deepanjan Datta, Sudeb Dasgupta	Modeling of Leakage Current Mechanisms in Nanoscale DG MOSFET and its Application to Low Power SRAM Design.	JCP	2008	DBLP DOI BibTeX RDF
1	Hyunwoo Nho, Sei-Seung Yoon, S. Simon Wong, Seong-Ook Jung	Numerical Estimation of Yield in Sub-100-nm SRAM Design Using Monte Carlo Simulation.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Ya-Chun Lai, Shi-Yu Huang	A Resilient and Power-Efficient Automatic-Power-Down Sense Amplifier for SRAM Design.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Behzad Ebrahimi, Saeed Zeinolabedinzadeh, Ali Afzali-Kusha	Low Standby Power and Robust FinFET Based SRAM Design.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin	An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing.	VTS	2008	DBLP DOI BibTeX RDF	write driver, design-for-diagnosis, diagnosis, SRAM
1	Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang	Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Hao-I Yang, Ssu-Yun Lai, Wei Hwang	Low-power floating bitline 8-T SRAM design with write assistant circuits.	SoCC	2008	DBLP DOI BibTeX RDF
1	Mohamed H. Abu-Rahma, Kinshuk Chowdhury, Joseph Wang, Zhiqin Chen, Sei Seung Yoon, Mohab Anis	A methodology for statistical estimation of read access yield in SRAMs.	DAC	2008	DBLP DOI BibTeX RDF	access failure, random variations, memory, variability, statistical modeling, yield, SRAM, worst-case
1	Michael Yap San Min, Philippe Maurine, Magali Bastian, Michel Robert	A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM.	DELTA	2008	DBLP DOI BibTeX RDF	dummy bitline driver, self-timed memory, low power, SRAM, statistical design
1	Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim	Circuit techniques for ultra-low power subthreshold SRAMs.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Amith Singhee, Jiajing Wang, Benton H. Calhoun, Rob A. Rutenbar	Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Sachin S. Sapatnekar	Adapting to the times [review of Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice (Wang, A. and Naffziger, S., Eds.; 2008)].	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF
1	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Florian Bauer, Georg Georgakos, Doris Schmitt-Landsiedel	A Design Space Comparison of 6T and 8T SRAM Core-Cells.	PATMOS	2008	DBLP DOI BibTeX RDF
1	Tamer Cakici, Keejong Kim, Kaushik Roy	FinFET Based SRAM Design for Low Standby Power Applications.	ISQED	2007	DBLP DOI BibTeX RDF
1	Gregory K. Chen, David Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim	Yield-driven near-threshold SRAM design.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Qikai Chen, Arjun Guha, Kaushik Roy	An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi	Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Chua-Chin Wang, Ching-Li Lee, Wun-Ji Lin	A 4-Kb low power 4-T SRAM design with negative word-line gate drive.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif	Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events.	DAC	2006	DBLP DOI BibTeX RDF	statistical performance analysis, SRAM, yield prediction
1	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment.	DATE	2006	DBLP DOI BibTeX RDF
1	Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park, Rouwaida Kanj, Sani R. Nassif	System-Level SRAM Yield Enhancement.	ISQED	2006	DBLP DOI BibTeX RDF
1	R. Venkatraman, R. Castagnetti, S. Ramesh	The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability.	ISQED	2006	DBLP DOI BibTeX RDF
1	Shengqi Yang, Wayne Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie	Low-leakage robust SRAM cell design for sub-100nm technologies.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Joohee Kim, Marios C. Papaefthymiou	Constant-load energy recovery memory for efficient high-speed operation.	ISLPED	2004	DBLP DOI BibTeX RDF	adiabatic circuitry, charge recovery, cache memories, on-chip memories, low-power computing, low-energy design
1	Vijay Degalahal, Narayanan Vijaykrishnan, Mary Jane Irwin	Analyzing Soft Errors in Leakage Optimized SRAM Design.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Hong-Yi Huang, Hsuan-Yi Su	Low-power 2P2N SRAM with column hidden refresh.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Jeyran Hezavei, Narayanan Vijaykrishnan, Mary Jane Irwin	A comparative study of power efficient SRAM designs.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF	low power, decoder, SRAM
1	Basabi Bhaumik, Pravas Pradhan, G. S. Visweswaran, Rajamohan Varambally, Anand Hardi	A Low Power 256 KB SRAM Design.	VLSI Design	1999	DBLP BibTeX RDF
1	Mankoo Lee, Wing-Il Sze, Chii-ming M. Wu	Static Noise Margin and Soft-Error Rate Simulations for Thin Film Transistor Cell Stability in a 4 Mbit SRAM Design.	ISCAS	1995	DBLP BibTeX RDF
1	F. L. Vargas, Michael Nicolaidis	SEU-Tolerant SRAM Design Based on Current Monitoring.	FTCS	1994	DBLP DOI BibTeX RDF