| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Pingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatnekar |
Optimized 3D Network-on-Chip Design Using Simulated Allocation.  |
ACM Trans. Design Autom. Electr. Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sachin S. Sapatnekar |
Editorial. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Saket Gupta, Sachin S. Sapatnekar |
GNOMO: Greater-than-NOMinal Vdd operation for BTI mitigation. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianxin Fang, Sachin S. Sapatnekar |
The impact of hot carriers on timing in large circuits. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Baktash Boghrati, Sachin S. Sapatnekar |
Incremental power network analysis using backward random walks. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Saket Gupta, Sachin S. Sapatnekar |
BTI-aware design using variable latency units. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sachin S. Sapatnekar |
Editorial. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar |
Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Pingqiang Zhou, Jieming Yin, Antonia Zhai, Sachin S. Sapatnekar |
NoC frequency scaling with flexible-pipeline routers. |
ISLPED |
2011 |
DBLP BibTeX RDF |
|
| 1 | Sachin S. Sapatnekar |
The whys and hows of thermal management. |
ISLPED |
2011 |
DBLP BibTeX RDF |
|
| 1 | Pingqiang Zhou, Dong Jiao, Chris H. Kim, Sachin S. Sapatnekar |
Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network. |
CICC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaeha Kung, Inhak Han, Sachin S. Sapatnekar, Youngsoo Shin |
Thermal signature: a simple yet accurate thermal index for floorplan optimization. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianxin Fang, Sachin S. Sapatnekar |
Accounting for inherent circuit resilience and process variations in analyzing gate oxide reliability. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Baktash Boghrati, Sachin S. Sapatnekar |
A scaled random walk solver for fast power grid analysis. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | T. Kolpe, Antonia Zhai, Sachin S. Sapatnekar |
Enabling improved power management in multicore processors through clustered DVFS. |
DATE |
2011 |
DBLP BibTeX RDF |
|
| 1 | Sachin S. Sapatnekar |
Editorial. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Qunzeng Liu, Sachin S. Sapatnekar |
Capturing Post-Silicon Variations Using a Representative Critical Path. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianxin Fang, Sachin S. Sapatnekar |
Scalable methods for the analysis and optimization of gate oxide breakdown. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yaoguang Wei, Sachin S. Sapatnekar |
Dummy fill optimization for enhanced manufacturability. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
routing, design for manufacturability, chemical-mechanical polishing, dummy fill |
| 1 | Sachin S. Sapatnekar |
Adding a new dimension to physical design. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
3D circuits, physical design |
| 1 | Sachin S. Sapatnekar (eds.) |
Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010 |
DAC |
2010 |
DBLP BibTeX RDF |
|
| 1 | Baktash Boghrati, Sachin S. Sapatnekar |
Incremental solution of power grids using random walks. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Saket Gupta, Sachin S. Sapatnekar |
Current source modeling in the presence of body bias. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Pingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatnekar |
Application-specific 3D Network-on-Chip design using simulated allocation. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yaoguang Wei, Jiang Hu, Frank Liu, Sachin S. Sapatnekar |
Physical design techniques for optimizing RTA-induced variations. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Haifeng Qian, Sachin S. Sapatnekar |
Fast Poisson solvers for thermal analysis. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Qunzeng Liu, Sachin S. Sapatnekar |
A Framework for Scalable Postsilicon Statistical Delay Prediction Under Process Variations. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan |
Fast and Accurate Statistical Criticality Computation Under Process Variations. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang |
A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sachin S. Sapatnekar |
Technical perspective - Where the chips may fall. |
Commun. ACM |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar |
Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity. |
IEEE Design & Test of Computers |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Qunzeng Liu, Sachin S. Sapatnekar |
Synthesizing a representative critical path for post-silicon delay prediction. |
ISPD |
2009 |
DBLP DOI BibTeX RDF |
post-silicon optimization, representative critical path |
| 1 | Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar |
Adaptive techniques for overcoming performance degradation due to aging in digital circuits. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sachin S. Sapatnekar |
Addressing thermal and power delivery bottlenecks in 3D circuits. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar |
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yong Zhan, Sanjay V. Kumar, Sachin S. Sapatnekar |
Thermally Aware Design. |
Foundations and Trends in Electronic Design Automation |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yong Zhan, Sachin S. Sapatnekar |
Automated module assignment in stacked-Vdd designs for high-efficiency power delivery. |
JETC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar |
A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaskirat Singh, Sachin S. Sapatnekar |
A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter Variations. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Shrirang K. Karandikar, Sachin S. Sapatnekar |
Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Haifeng Qian, Sachin S. Sapatnekar |
Stochastic Preconditioning for Diagonally Dominant Matrices. |
SIAM J. Scientific Computing |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar |
Body Bias Voltage Computations for Process and Temperature Compensation. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim |
Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim |
Stack Sizing for Optimal Current Drivability in Subthreshold Circuits. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sachin S. Sapatnekar |
Building your yield of dreams. |
IEEE Design & Test of Computers |
2008 |
DBLP DOI BibTeX RDF |
nanoscale, modeling variations, CMOS, yield, design for manufacturability, DFM |
| 1 | Sachin S. Sapatnekar |
Adapting to the times [review of Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice (Wang, A. and Naffziger, S., Eds.; 2008)]. |
IEEE Design & Test of Computers |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Tianpei Zhang, Sachin S. Sapatnekar |
Buffering global interconnects in structured ASIC design. |
Integration |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sanjay V. Kumar, Chandramouli V. Kashyap, Sachin S. Sapatnekar |
A framework for block-based timing sensitivity analysis. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
pruning, variations, reordering, slacks, arrival times |
| 1 | Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang |
A progressive-ILP based routing algorithm for cross-referencing biochips. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
progressive-ILP, routing, microfluidics, biochip |
| 1 | Sachin S. Sapatnekar, Eshel Haritan, Kurt Keutzer, Anirudh Devgan, Desmond Kirkpatrick, Stephen Meier, Duaine Pryor, Tom Spyrou |
Reinventing EDA with manycore processors. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
parallelization, CAD, software, multicore, EDA, speedup, manycore |
| 1 | Hongliang Chang, Sachin S. Sapatnekar |
Prediction of leakage power under process uncertainties. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
process variation, yield, leakage, Circuit |
| 1 | Krishnendu Chakrabarty, Sachin S. Sapatnekar |
Editorial to special issue DAC 2006. |
JETC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Gustavo de Veciana, Marcello Lajolo, Chen He, Enrico Macii, Sachin S. Sapatnekar |
In Memoriam: Margarida F. Jacome. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yong Zhan, Sachin S. Sapatnekar |
High-Efficiency Green Function-Based Thermal Simulation Algorithms. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Tianpei Zhang, Sachin S. Sapatnekar |
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Sachin S. Sapatnekar |
Book Review: An Assay of Biochips. |
IEEE Design & Test of Computers |
2007 |
DBLP DOI BibTeX RDF |
LoC systems, design automation, microfluidics, biochips, bioMEMS |
| 1 | Sachin S. Sapatnekar, Leon Stok |
DAC Highlights. |
IEEE Design & Test of Computers |
2007 |
DBLP DOI BibTeX RDF |
semiconductor industry, DAC, electronic design automation, automotive electronics, Design Automation Conference |
| 1 | Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi |
Probabilistic Congestion Prediction with Partial Blockages. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Sachin S. Sapatnekar |
Computer-aided design of 3d integrated circuits. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Felipe S. Marques, Leomar S. da Rosa Jr., Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis |
DAG based library-free technology mapping. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
library free synthesis, logic synthesis, technology mapping, switching theory, virtual libraries |
| 1 | Jie Gu, Sachin S. Sapatnekar, Chris H. Kim |
Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Brent Goplen, Sachin S. Sapatnekar |
Placement of 3D ICs with Thermal and Interlayer Via Considerations. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar |
NBTI-Aware Synthesis of Digital Circuits. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Qunzeng Liu, Sachin S. Sapatnekar |
Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar |
Module assignment for pin-limited designs under the stacked-Vdd paradigm. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan |
Clustering based pruning for statistical criticality computation under process variations. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Dmitry Bufistov, Jordi Cortadella, Michael Kishinevsky, Sachin S. Sapatnekar |
A general model for performance optimization of sequential systems. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Brent Goplen, Sachin S. Sapatnekar |
Placement of Thermal Vias in 3-D ICs Using Various Thermal Objectives. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Rupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar |
Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaskirat Singh, Sachin S. Sapatnekar |
Partition-Based Algorithm for Power Grid Design Using Locality. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze |
Accurate estimation of global buffer delay within a floorplan. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sachin S. Sapatnekar, Grant Martin |
DAC Highlights. |
IEEE Design & Test of Computers |
2006 |
DBLP DOI BibTeX RDF |
DAC, Design Automation Conference |
| 1 | Sachin S. Sapatnekar |
Book Reviews: Plumbing the Depths of Leakage. |
IEEE Design & Test of Computers |
2006 |
DBLP DOI BibTeX RDF |
nanometer CMOS technology, leakage |
| 1 | Keith A. Bowman, Michael Orshansky, Sachin S. Sapatnekar |
Tutorial II: Variability and Its Impact on Design. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar |
Impact of NBTI on SRAM Read Stability and Design for Reliability. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
Static Noise Margin (SNM), Reaction-Diffusion (R-D) Model, Cache, SRAM, Negative Bias Temperature Instability (NBTI) |
| 1 | Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar |
Comparing simulation techniques for microarchitecture-aware floorplanning. |
ISPASS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Vidyasagar Nookala, David J. Lilja, Sachin S. Sapatnekar |
Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
floorplanning, microarchitecture, transient analysis |
| 1 | Leomar S. da Rosa Jr., Felipe S. Marques, Tiago Muller Gil Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis |
Fast disjoint transistor networks from BDDs. |
SBCCI |
2006 |
DBLP DOI BibTeX RDF |
PTL, unateness, BDDs, switch theory, CMOS gates |
| 1 | Jaskirat Singh, Sachin S. Sapatnekar |
Statistical timing analysis with correlated non-gaussian parameters using independent component analysis. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
non-Gaussian, independent component analysis, statistical timing, moment matching |
| 1 | John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim |
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
subthreshold logic, ultra-low power design, logical effort |
| 1 | Yong Zhan, Brent Goplen, Sachin S. Sapatnekar |
Electrothermal analysis and optimization techniques for nanoscale integrated circuits. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Tianpei Zhang, Yong Zhan, Sachin S. Sapatnekar |
Temperature-aware routing in 3D ICs. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yong Zhan, Yan Feng, Sachin S. Sapatnekar |
A fixed-die floorplanning algorithm using an analytical approach. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar |
Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
Nonlinear Programming Problem (NLPP), daptive Body Bias (ABB), temperature variations, delay, process variations, leakage, enumeration |
| 1 | Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar |
An analytical model for negative bias temperature instability. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar |
Power grid analysis using random walks. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar |
Early-stage power grid analysis for uncertain working modes. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaskirat Singh, Sachin S. Sapatnekar |
Congestion-aware topology optimization of structured power/ground networks. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Hongliang Chang, Sachin S. Sapatnekar |
Statistical timing analysis under spatial correlations. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang |
A predictive distributed congestion metric with application to technology mapping. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Rupesh S. Shelar, Sachin S. Sapatnekar |
BDD decomposition for delay oriented pass transistor logic synthesis. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar |
Gate oxide leakage and delay tradeoffs for dual-T/sub ox/ circuits. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Shrirang K. Karandikar, Sachin S. Sapatnekar |
Fast comparisons of circuit implementations. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Sachin S. Sapatnekar |
Designing "Vary" Good Circuitry. |
IEEE Design & Test of Computers |
2005 |
DBLP DOI BibTeX RDF |
optimization, VLSI, statistical analysis, timing analysis, power analysis, CAD tools |
| 1 | Sachin S. Sapatnekar |
An EDA compendium. |
IEEE Design & Test of Computers |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Sachin S. Sapatnekar |
Empowering the designer. |
IEEE Design & Test of Computers |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Sachin S. Sapatnekar, Kevin J. Nowka |
Guest Editors' Introduction: New Dimensions in 3D Integration. |
IEEE Design & Test of Computers |
2005 |
DBLP DOI BibTeX RDF |
wafer stacking, silicon processing, FPGA, architecture, CAD tools, 3D integration, 3D design |
| 1 | Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar |
Placement and Routing in 3D Integrated Circuits. |
IEEE Design & Test of Computers |
2005 |
DBLP DOI BibTeX RDF |
VLSI, Placement and routing |
| 1 | Felipe S. Marques, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis |
A new approach to the use of satisfiability in false path detection. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
unateness, satisfiability, false paths |
| 1 | Brent Goplen, Sachin S. Sapatnekar |
Thermal via placement in 3D ICs. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
3-D VLSI, thermal gradient, thermal optimization, thermal via, routing, placement, temperature, finite element analysis, 3-D IC |
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")