Search results for "Sai-Weng Sin"

Hits ?▲	Authors	Title	Venue	Year	Link
1	U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration.	ESSCIRC	2011	DBLP DOI BibTeX RDF
1	He Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti	A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS.	ISSCC	2011	DBLP DOI BibTeX RDF
1	Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti	A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS.	J. Solid-State Circuits	2010	DBLP DOI BibTeX RDF
1	U-Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti	Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	He Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators.	ICECS	2010	DBLP DOI BibTeX RDF
1	Guohe Yin, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Zhihua Wang	An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications.	ICECS	2010	DBLP DOI BibTeX RDF
1	Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Sai-Weng Sin, U-Fat Chio, Seng-Pan U., Rui Paulo Martins	Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	He Gong Wei, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	A novel low-voltage cross-coupled passive sampling branch for reset- and switched-opamp circuits.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuits.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Seng-Pan U., Sai-Weng Sin, Rui Paulo Martins	Exact spectra analysis of sampled signals with jitter-induced nonuniformly holding effects.	IEEE T. Instrumentation and Measurement	2004	DBLP DOI BibTeX RDF
1	Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems.	ISCAS	2004	DBLP BibTeX RDF
1	Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, José E. Franca	Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output.	ISCAS	2003	DBLP DOI BibTeX RDF

Publications of "Sai-Weng Sin" ( http://dblp.L3S.de/Authors/Sai-Weng_Sin )